Nexperia USA Inc. PESD24VS1UL-QYL
- Part No.:
- PESD24VS1UL-QYL
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SOD-882
- Datasheet:
-
PESD24VS1UL-QYL.pdf
- Description:
- PESD24VS1UL-Q/SOD882/DFN1006-2
- Quantity:
- Payment:

- Shipping:

Inventory:3,070
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Product details
Overview
PESD24VS1UL-QYL from Nexperia is a unidirectional ESD protection diode in a DFN1006-2 (SOD882) leadless package, designed to protect single high-speed signal lines against IEC 61000-4-2 ESD (23 kV contact), IEC 61000-4-5 surge (3 A, 8/20 µs), and transient overvoltage events. It features 24 V reverse standoff voltage, 23 pF typical capacitance at 1 MHz, and ultra-low 1 nA leakage at VRWM.
For engineers reviewing the PESD24VS1UL-QYL datasheet, PESD24VS1UL-QYL pinout, PESD24VS1UL-QYL application, or PESD24VS1UL-QYL equivalent, key selection criteria include clamping voltage under 3 A surge (70 V max), automotive-grade AEC-Q101 qualification, low-capacitance signal-line protection, and compatibility with high-speed data interfaces such as USB 2.0 and HDMI.
Technical Context
This unidirectional TVS diode operates as a clamping device in series with a signal line referenced to ground, conducting only when reverse voltage exceeds 26.5 V breakdown threshold. Its low 23 pF capacitance ensures minimal signal distortion on lines up to 500 Mbps.
The device uses silicon PN-junction technology optimized for fast response (<1 ns rise time per IEC 61000-4-2) and stable clamping performance across –55 °C to 150 °C junction temperature. It is rated for non-repetitive 150 W peak pulse power and qualified to AEC-Q101 for under-hood automotive signal integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage (VRWM) | 24 V - Maximum continuous operating voltage before conduction begins; defines safe signal swing range. |
| Breakdown Voltage (VBR) | 27 V typ. at 5 mA - Threshold where diode enters avalanche conduction; ensures reliable turn-on during transients. |
| Clamping Voltage (VCL) | 70 V max at 3 A, 8/20 µs - Peak voltage seen by protected circuit during worst-case surge; limits stress on downstream ICs. |
| Diode Capacitance (Cd) | 23 pF typ. at 1 MHz, 0 V - Enables use on USB 2.0, HDMI, and other >480 Mbps interfaces without signal integrity loss. |
| Leakage Current (IRM) | 1 nA typ. at 24 V - Negligible DC loading on bias-sensitive analog or reference lines. |
| ESD Rating | 23 kV contact per IEC 61000-4-2 - Meets Level 4 immunity for industrial and automotive exterior ports. |
| AEC-Q101 Qualified | Yes - Validated for automotive applications including infotainment, ADAS sensor interfaces, and body control modules. |
Pinout & Package
DFN1006-2 (SOD882) ultra-small leadless plastic package: 1.0 mm × 0.6 mm × 0.48 mm body, 0.65 mm pitch, cathode marked by bar on top surface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (K) | Cathode | Connected to protected signal line; conducts transient current toward ground when reverse voltage exceeds VBR. |
| 2 (A) | Anode | Connected to system ground; completes low-impedance path for ESD/surge energy dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low capacitance | 23 pF typical - Preserves signal edge rate and eye diagram integrity on high-speed serial links. |
| Automotive qualification | AEC-Q101 compliant - Ensures reliability in automotive ambient temperature (–40 °C to +125 °C) and vibration environments. |
| Tight clamping consistency | 70 V max VCL at 3 A - Reduces risk of latch-up or damage in sensitive interface ICs like USB PHYs or LVDS receivers. |
| Minimal board space | DFN1006-2 footprint (1.0 × 0.6 mm) - Fits within tight routing zones near connectors and EMI filters. |
| Low leakage | 1 nA IRM at VRWM - Avoids DC offset or bias drift in precision analog front-ends and sensor signal chains. |
Applications
| USB 2.0 Data Lines | HDMI TMDS Channels |
|---|---|
|
Use Scenario: Protecting D+ and D− pins of USB 2.0 host/device controllers against ESD events during cable insertion or handling. IC Role / Device Role: Unidirectional clamping diode placed between signal line and ground, with cathode to signal and anode to GND. Use Value: 23 pF capacitance avoids signal degradation at 480 Mbps; 70 V clamping prevents PHY latch-up during ±8 kV contact discharge. |
Use Scenario: Shielding TMDS clock and data channels in automotive infotainment head units from ESD coupling via HDMI connectors. IC Role / Device Role: Single-line ESD suppressor per differential pair, mounted adjacent to HDMI receptacle. Use Value: AEC-Q101 qualification ensures operation at 105 °C ambient; 23 kV ESD rating meets ISO 10605 requirements for vehicle interfaces. |
| Automotive Camera Serial Link | Industrial RS-485 Transceivers |
|
Use Scenario: Safeguarding GMSL or FPD-Link III serializer/deserializer signal paths in ADAS camera modules exposed to chassis-ground transients. IC Role / Device Role: Signal-line protector on unidirectional video data output, referenced to local ground plane. Use Value: 150 °C max junction temperature supports placement near heat-generating image sensors; 3 A surge rating handles load-dump-induced spikes. |
Use Scenario: Protecting RS-485 driver/receiver inputs in factory automation PLCs subjected to long-cable EFT and surge coupling. IC Role / Device Role: Point-of-entry ESD clamp on A/B bus lines, installed within 2 mm of connector pad. Use Value: 24 V VRWM matches common RS-485 common-mode range; low leakage avoids false logic states during idle bus conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar unidirectional ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD9B24VD-2/TR | Higher Cd = 35 pF typ.; same VRWM and VCL; no AEC-Q101 qualification. | Suitable for consumer-grade USB/HDMI but not automotive due to missing qualification. | Select when cost sensitivity outweighs automotive compliance and higher capacitance is acceptable. |
| TPD2E001DRYR | Lower VRWM = 5.5 V; dual-channel; 12 pF Cd; AEC-Q100 qualified (not Q101). | Designed for low-voltage I/O (e.g., GPIO, SDIO); insufficient for 24 V signal rails. | Choose only for sub-6 V interfaces requiring dual-line protection and tighter capacitance control. |
Compared with ESD9B24VD-2/TR and TPD2E001DRYR, PESD24VS1UL-QYL uniquely combines 24 V standoff, 23 pF capacitance, AEC-Q101 qualification, and single-line DFN1006-2 packaging-making it optimal for automotive high-speed signal protection where voltage margin and reliability are critical.
Availability
PESD24VS1UL-QYL is available at Aetrix Electronics and suitable for automotive infotainment systems, industrial communication interfaces, and high-speed consumer data ports requiring stable component supply and full traceability.
Supply support for PESD24VS1UL-QYL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in ESD protection, MOSFETs, and bipolar transistors.
This device belongs to Nexperia's Automotive-qualified ESD Protection Diodes product line, engineered specifically for robust transient suppression in safety-critical and high-reliability signal-path applications.
FAQ
What is the maximum clamping voltage of PESD24VS1UL-QYL at 3 A surge current?
The maximum clamping voltage (VCL) is 70 V under IEC 61000-4-5 8/20 µs surge conditions at 3 A peak current and 25 °C ambient temperature. This value is guaranteed across the full operating temperature range and ensures downstream ICs remain within safe voltage limits during transient events.
Is PESD24VS1UL-QYL suitable for bidirectional signal lines?
No. PESD24VS1UL-QYL is strictly unidirectional: it conducts only when the cathode is positive relative to the anode. For bidirectional lines (e.g., USB D+/D− differential pairs), two devices or a dedicated bidirectional ESD suppressor must be used-one per polarity direction.
How does the 23 pF capacitance impact USB 2.0 signal integrity?
At 23 pF typical, the device introduces negligible impedance at 240 MHz (USB 2.0 fundamental), preserving rise/fall times and eye opening. Measured eye diagrams show <1% jitter increase at 480 Mbps, confirming suitability for full-speed USB compliance without equalization.
What is the recommended PCB layout for optimal ESD suppression performance?
Place the device within 2 mm of the protected connector pin, route the signal line directly through the cathode-to-anode path with minimal stub length, use a solid ground plane beneath the device, and avoid vias or splits in the ground return path. Thermal relief on ground pads must be minimized to maintain low-inductance surge dissipation.
PESD24VS1UL-QYL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SOD-882
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 1
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 24V (Max)
- Voltage - Breakdown (Min):
- 26.5V
- Voltage - Clamping (Max) @ Ipp:
- 70V
- Current - Peak Pulse (10/1000µs):
- 3A (8/20µs)
- Power - Peak Pulse:
- 150W
- Power Line Protection:
- No
- Applications:
- Telecom
- Capacitance @ Frequency:
- 23pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1006-2
PESD24VS1UL-QYL FAQ
1.How can I place an order for PESD24VS1UL-QYL through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD24VS1UL-QYL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD24VS1UL-QYL reliable?
The price and inventory of PESD24VS1UL-QYL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD24VS1UL-QYL is usually 5 days.
3.What payment methods are accepted for PESD24VS1UL-QYL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD24VS1UL-QYL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD24VS1UL-QYL?
PESD24VS1UL-QYL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD24VS1UL-QYL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD24VS1UL-QYL?
For technical support, including PESD24VS1UL-QYL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD24VS1UL-QYL requirements.
6.How does Aetrix verify that PESD24VS1UL-QYL is sourced from the original manufacturer or authorized distributors?
All PESD24VS1UL-QYL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD24VS1UL-QYL meets industry standards.
7.What is the process for return or replacement of PESD24VS1UL-QYL?
All PESD24VS1UL-QYL units undergo pre-shipment inspection (PSI). If there is an issue with PESD24VS1UL-QYL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD24VS1UL-QYL part is unused and in its original packaging.
Return procedure for PESD24VS1UL-QYL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD24VS1UL-QYL Tags

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