Nexperia USA Inc. PESD2ETH100T-QR
- Part No.:
- PESD2ETH100T-QR
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- -
- Datasheet:
-
PESD2ETH100T-QR.pdf
- Description:
- AUTOMOTIVE LOW SPEED IVN
- Quantity:
- Payment:

- Shipping:

Inventory:2,555
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Product details
Overview
PESD2ETH100T-QR from Nexperia is a dual-line automotive ESD protection diode in SOT23 package, fully compliant with OPEN Alliance 100BASE-T1 specification, featuring 100 V minimum trigger voltage (Vt1), <3 pF capacitance, and 30 kV IEC 61000-4-2 contact discharge rating - designed to safeguard differential Ethernet bus lines in vehicle domain controllers and ADAS camera links.
For engineers reviewing the PESD2ETH100T-QR datasheet, PESD2ETH100T-QR pinout, PESD2ETH100T-QR application, or PESD2ETH100T-QR equivalent, key selection criteria include bidirectional clamping symmetry, sub-3 pF line-to-line capacitance matching, AEC-Q101 qualification, and verified 1000-cycle OPEN Alliance ESD endurance at ±30 kV.
Technical Context
This device implements a common-cathode dual-diode architecture optimized for high-speed automotive Ethernet (100BASE-T1) signal integrity: it provides symmetrical positive/negative clamping with dynamic resistance ≤0.44 Ω and holds below 28 V after triggering, enabling robust transient suppression without signal distortion on differential pairs.
Its design satisfies OPEN Alliance's four mandatory EMC test categories - return loss (Sdd11), insertion loss (Sdd21), differential-to-common-mode rejection (Ssd21), and RF clamping - with no degradation after 20× ±8 kV ISO 10605 stress events, confirming long-term reliability in harsh automotive environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Trigger Voltage (Vt1) | 100 V min - ensures immunity to normal 24 V automotive bus transients while activating only during ESD events |
| Diode Capacitance (Cd) | 2.5–3 pF - maintains signal integrity up to 100 MHz for 100BASE-T1 (100 Mbps) without skew or attenuation |
| Capacitance Matching (ΔCd/Cd) | ≤0.5% - guarantees balanced differential signaling and minimizes common-mode conversion |
| ESD Withstand (IEC 61000-4-2) | 30 kV contact discharge - exceeds OPEN Alliance requirement for 1000 cycles without parameter shift |
| Reverse Standoff (VRWM) | 24 V - compatible with automotive 12 V/24 V supply rails and PHY-level voltage margins |
| Holding Voltage (Vh) | 28 V - sustains clamping state post-trigger to prevent latch-up and ensure clean recovery |
| Dynamic Resistance (Rdyn) | 0.44 Ω - limits clamping voltage overshoot under 70 A TLP pulses, reducing PHY stress |
Pinout & Package
SOT23 plastic surface-mount package (2.9 mm × 1.3 mm × 1.0 mm, 1.9 mm lead pitch), qualified per AEC-Q101, suitable for reflow and wave soldering per JEDEC J-STD-020/001.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | K (cathode) | Connects to BI_DA+ line; forms first ESD path to common cathode |
| 2 | K (cathode) | Connects to BI_DA− line; forms second ESD path to common cathode |
| 3 | CC (common cathode) | Shared low-impedance return path to ground plane; enables matched dual-line clamping |
Key Features
| Feature | Design Value |
|---|---|
| OPEN Alliance 100BASE-T1 compliance | Passes all four mandatory EMC tests (Sdd11/Sdd21/Ssd21/RF clamping) with zero performance drift after repetitive ESD stress |
| Bidirectional clamping symmetry | Identical Vt1 (100 V min) and VCL response on both pins ensures equal protection for + and − data lines |
| Ultra-low capacitance matching | ΔCd/Cd ≤0.5% eliminates differential skew and preserves 100BASE-T1 eye diagram integrity |
| AEC-Q101 qualification | Rated for −55 °C to +150 °C junction temperature, supporting under-hood and ADAS module deployment |
| Common-cathode dual-diode topology | Single-package solution reduces PCB area by 40% vs. discrete dual-diode layouts while improving layout symmetry |
Applications
| Automotive 100BASE-T1 Ethernet | ADAS Camera Link Protection |
|---|---|
|
Use Scenario: High-speed data transmission between domain controller and Ethernet-enabled radar/sensor modules in vehicles. IC Role / Device Role / Timing Role: Dual-line ESD clamp placed adjacent to PHY IC to suppress ±30 kV transients before signal enters receiver. Use Value: Prevents PHY latch-up or damage during assembly ESD events and real-world cable hot-plug scenarios, maintaining >99.9% link uptime. |
Use Scenario: Shielded twisted-pair connection from front-facing camera to central ADAS processor over 100BASE-T1. IC Role / Device Role / Timing Role: Line-side transient suppressor mounted at connector entry point to shunt ESD energy to chassis ground. Use Value: Maintains <0.5 dB insertion loss at 65 MHz and passes OPEN Alliance return loss limits, preserving image sync timing accuracy. |
| LVDS Automotive Video Links | Vehicle Infotainment Backhaul |
|
Use Scenario: Differential video transport from display module to head unit using LVDS-based protocols (e.g., FPD-Link III). IC Role / Device Role / Timing Role: Low-capacitance protector on each LVDS pair to avoid signal edge degradation and jitter accumulation. Use Value: Cd <3 pF and ΔCd/Cd ≤0.5% prevent pixel clock skew and reduce bit error rate (BER) in 1.5 Gbps video streams. |
Use Scenario: In-vehicle infotainment backbone connecting touchscreen, audio processor, and telematics unit via 100BASE-T1. IC Role / Device Role / Timing Role: ESD guard on both differential lanes of multi-drop Ethernet segment operating in noisy cabin environment. Use Value: Survives 1000× ±30 kV discharges per OPEN Alliance spec, ensuring field-replaceable module longevity across 15-year vehicle lifecycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-line automotive ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor NUF2221MUTAG | Higher Cd = 5.5 pF; lower Vt1 = 12 V; not OPEN Alliance certified | Targeted at general-purpose USB/LVDS, not validated for 100BASE-T1 EMC behavior | Select only if cost sensitivity outweighs 100BASE-T1 compliance and signal integrity requirements |
| Vishay VEML6075Y3 | UV sensor IC - functionally unrelated; misidentified as ESD device in some distributor listings | Not an ESD protector; incompatible circuit role and pinout | Exclude from consideration - incorrect functional category and no ESD capability |
Compared with NUF2221MUTAG and VEML6075Y3, PESD2ETH100T-QR uniquely delivers OPEN Alliance–validated 100BASE-T1 compliance, sub-3 pF matched capacitance, and AEC-Q101 qualification - making it the only viable choice for production automotive Ethernet nodes requiring guaranteed EMC robustness and signal fidelity.
Availability
PESD2ETH100T-QR is available at Aetrix Electronics and suitable for automotive domain controllers, ADAS camera modules, and infotainment backhaul systems requiring stable component supply, long-lifecycle support, and traceable AEC-Q101–qualified parts.
Supply support for PESD2ETH100T-QR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete and logic devices for automotive, industrial, and computing markets.
PESD2ETH100T-QR belongs to Nexperia's Automotive ESD Protection portfolio, engineered specifically for high-speed differential bus standards including 100BASE-T1, 1000BASE-T1, and LVDS - prioritizing signal integrity, EMC compliance, and AEC-Q101 reliability.
FAQ
Is PESD2ETH100T-QR pin-compatible with PESD2ETH100T-Q?
Yes - PESD2ETH100T-QR is the tape-and-reel variant of PESD2ETH100T-Q, sharing identical SOT23 pinout (Pin 1 = K, Pin 2 = K, Pin 3 = CC), electrical characteristics, and mechanical dimensions. The "R" suffix denotes packaging format only, not functional revision.
Does this device support 1000BASE-T1 (1 Gbps) applications?
No - PESD2ETH100T-QR is qualified and tested exclusively for 100BASE-T1 (100 Mbps). Its 3 pF capacitance and S-parameter performance meet OPEN Alliance limits up to 100 MHz, but insertion loss and return loss exceed thresholds above 200 MHz required for 1000BASE-T1.
What is the recommended PCB layout for optimal ESD performance?
Place PESD2ETH100T-QR within 3 mm of the connector, route differential traces symmetrically to Pin 1 and Pin 2, connect Pin 3 directly to a low-inductance chassis ground plane via multiple vias, and avoid stubs or splits in the ground reference to maintain <0.5% capacitance matching.
Can this device be used in non-automotive applications like industrial Ethernet?
Yes - its 30 kV ESD rating, 24 V VRWM, and low capacitance make it suitable for industrial 100BASE-T1 deployments, but AEC-Q101 qualification is not required there. Note that OPEN Alliance test validation applies only to automotive use cases; industrial EMC standards (e.g., IEC 61000-4-5) require separate system-level verification.
PESD2ETH100T-QR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- -
- Unidirectional Channels:
- -
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- -
- Voltage - Breakdown (Min):
- -
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- -
- Applications:
- -
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
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- Mounting Type:
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- Supplier Device Package:
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PESD2ETH100T-QR FAQ
1.How can I place an order for PESD2ETH100T-QR through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD2ETH100T-QR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD2ETH100T-QR reliable?
The price and inventory of PESD2ETH100T-QR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD2ETH100T-QR is usually 5 days.
3.What payment methods are accepted for PESD2ETH100T-QR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD2ETH100T-QR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD2ETH100T-QR?
PESD2ETH100T-QR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD2ETH100T-QR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD2ETH100T-QR?
For technical support, including PESD2ETH100T-QR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD2ETH100T-QR requirements.
6.How does Aetrix verify that PESD2ETH100T-QR is sourced from the original manufacturer or authorized distributors?
All PESD2ETH100T-QR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD2ETH100T-QR meets industry standards.
7.What is the process for return or replacement of PESD2ETH100T-QR?
All PESD2ETH100T-QR units undergo pre-shipment inspection (PSI). If there is an issue with PESD2ETH100T-QR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD2ETH100T-QR part is unused and in its original packaging.
Return procedure for PESD2ETH100T-QR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD2ETH100T-QR Tags

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