Nexperia USA Inc. PESD2ETH-AD/DG/B2X
- Part No.:
- PESD2ETH-AD/DG/B2X
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SC-74, SOT-457
- Datasheet:
-
PESD2ETH-AD/DG/B2X.pdf
- Description:
- PESD2ETH-AD - ULTRA LOW CAPACITA
- Quantity:
- Payment:

- Shipping:

Inventory:126,000
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Product details
Overview
PESD2ETH-AD from Nexperia is an ultra-low-capacitance double rail-to-rail ESD protection diode in SOT457 (TSOP6) package, designed to protect two high-speed automotive Ethernet data lines (e.g., 100BASE-T1) against ESD transients up to 23 kV (ISO 10605) and 12 kV (IEC 61000-4-2), with per-channel capacitance of 2.0–2.3 pF at 1 MHz and clamping voltage of 12.3 V at 3.5 A.
For engineers reviewing the PESD2ETH-AD datasheet, PESD2ETH-AD pinout, PESD2ETH-AD application, or PESD2ETH-AD equivalent, this device is selected for low-signal-distortion ESD protection in AEC-Q101-compliant automotive serial interfaces where sub-2.5 pF channel capacitance, rail-to-rail bidirectional clamping, and supply-independent protection are required.
Technical Context
The PESD2ETH-AD integrates three ESD protection elements: two ultra-low-capacitance rail-to-rail diodes (pins 1/6 ↔ GND and pins 3/4 ↔ GND) plus one dedicated Zener diode (pin 5 ↔ GND) enabling protection even when VCC is unpowered. Its architecture supports simultaneous bidirectional clamping on both I/O channels without DC bias dependency.
It delivers dynamic resistance of 0.83 Ω (positive clamping) and 0.62 Ω (negative clamping), with reverse standoff voltage of 5.5 V and breakdown voltage of 6–9 V, ensuring robust transient suppression while preserving signal integrity in 100 Mbps+ differential links such as BroadR-Reach PHY interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Capacitance (per channel) | 2.0–2.3 pF @ 1 MHz, 0 V - preserves signal rise/fall times in 100BASE-T1/LVDS links |
| Clamping Voltage | 12.3 V @ 3.5 A, 8/20 µs - limits transient overvoltage below IC damage threshold |
| ESD Rating | 12 kV contact (IEC 61000-4-2), 23 kV air (ISO 10605) - exceeds automotive EMC requirements |
| Reverse Standoff Voltage | 5.5 V - compatible with 3.3 V/5 V automotive data line biasing |
| Breakdown Voltage | 6–9 V - ensures reliable turn-on before system-level damage occurs |
| Dynamic Resistance | 0.83 Ω (positive), 0.62 Ω (negative) - minimizes voltage overshoot during fast transients |
| AEC-Q101 Qualified | Yes - validated for automotive temperature range (−55 °C to +150 °C) |
Pinout & Package
SOT457 (TSOP6) plastic surface-mounted package, 6-pin, 1.7 mm × 2.7 mm footprint, 0.95 mm pitch, 1.1 mm height - optimized for high-density automotive PCB layouts near connectors.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 6 | I/O 1 | Rail-to-rail ESD path for first differential pair; symmetric layout enables balanced routing |
| 3, 4 | I/O 2 | Rail-to-rail ESD path for second differential pair; dual-pin assignment reduces trace inductance |
| 2 | GND | Low-inductance ground return for all clamping paths; must connect directly to solid ground plane |
| 5 | VCC | Zener-based protection node; provides supply-independent clamping when VCC is absent or floating |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low channel capacitance | 2.0–2.3 pF enables <100BASE-T1 compliance without signal degradation or timing skew |
| Rail-to-rail bidirectional clamping | Protects both positive and negative transients on each I/O line without polarity constraints |
| Supply-independent protection | VCC pin connects to internal Zener; full ESD immunity maintained even during power-down states |
| AEC-Q101 qualification | Validated for automotive under-hood environments including thermal cycling and humidity exposure |
| Optimized for BroadR-Reach PHY | Pin mapping and layout guidelines align with TJA1100 and similar 100BASE-T1 transceivers |
Applications
| 100BASE-T1 Automotive Ethernet | Automotive LVDS Interfaces |
|---|---|
|
Use Scenario: Protection of differential pairs in automotive Ethernet PHYs (e.g., NXP TJA1100) connecting ADAS cameras and domain controllers. IC Role / Device Role / Timing Role: ESD transient suppressor placed immediately after common-mode choke and before PHY receiver inputs. Use Value: Prevents latch-up or oxide damage from ISO 10605 23 kV discharges while maintaining <100 ps signal distortion due to 2.2 pF capacitance. |
Use Scenario: Signal line protection in infotainment display links (e.g., MIPI D-PHY variants) operating at >600 Mbps. IC Role / Device Role / Timing Role: Rail-to-rail clamp on LVDS TX/RX pairs to absorb ESD events induced by connector mating/unmating. Use Value: Enables robust operation across −40 °C to +105 °C ambient with clamping voltage ≤12.3 V, avoiding false triggering or data corruption. |
| USB 2.0 Automotive | Automotive Sensor Data Links |
|
Use Scenario: ESD hardening of USB 2.0 ports in vehicle telematics modules exposed to user-accessible connectors. IC Role / Device Role / Timing Role: Dual-channel protection on D+/D− lines, placed adjacent to USB receptacle with minimal trace length. Use Value: Meets USB-IF ESD immunity requirements with 12 kV IEC 61000-4-2 rating and <2.5 pF loading to preserve 480 Mbps eye diagram integrity. |
Use Scenario: Protection of high-speed sensor outputs (e.g., radar ADC streams, camera serializers) routed through harnesses to ECUs. IC Role / Device Role / Timing Role: Point-of-entry protection on differential analog/digital sensor lines entering ECU housing. Use Value: Ensures functional safety compliance (ISO 26262 ASIL-B) via AEC-Q101 qualification and predictable clamping behavior under repeated 8/20 µs surges. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor ESD7L5.0DT5G | Single-channel, 5.0 V VRWM, 0.65 pF typical capacitance - lower capacitance but no rail-to-rail or VCC-assisted protection | Limited to single-line protection; requires external bias for bidirectional clamping; not AEC-Q101 qualified | Select only for non-automotive, single-ended, ultra-high-speed (<5 Gbps) applications where lowest possible capacitance is critical |
| Vishay VEML6030X01 | Not applicable - optical ambient light sensor, unrelated function and package | N/A - incorrect product category; excluded from functional comparison | Not a valid alternative; verify part number and function before selection |
Compared with ESD7L5.0DT5G, PESD2ETH-AD offers dual-channel rail-to-rail protection with supply-independent operation and AEC-Q101 qualification-critical for automotive 100BASE-T1-but trades 1.55 pF lower capacitance for integrated system-level robustness.
Availability
PESD2ETH-AD is available at Aetrix Electronics and suitable for automotive Ethernet PHY protection, LVDS display interface hardening, and USB 2.0 port ESD mitigation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for PESD2ETH-AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices with focus on efficiency, reliability, and miniaturization for automotive, industrial, and mobile markets.
PESD2ETH-AD belongs to Nexperia's automotive-grade ESD protection portfolio, engineered specifically for high-speed serial interfaces in vehicles-including 100BASE-T1, LVDS, and USB-where ultra-low capacitance and AEC-Q101 compliance are mandatory.
FAQ
What is the maximum peak pulse current the PESD2ETH-AD can handle?
The PESD2ETH-AD is rated for 3.5 A peak pulse current under IEC 61000-4-5 8/20 µs waveform conditions. This value is specified in the Limiting Values table and verified per IEC 60134 absolute maximum rating system, with derating applied above 85 °C ambient temperature.
Does PESD2ETH-AD require an external power supply to function?
No. The device provides full ESD protection even when VCC (pin 5) is unconnected or at 0 V, thanks to its internal Zener diode structure. Pin 5 enhances clamping performance when biased but is not mandatory for basic rail-to-rail protection of pins 1/3/4/6 relative to GND.
How does the dual-pin assignment (pins 1 & 6; pins 3 & 4) improve ESD performance?
Each I/O channel uses two parallel pins to halve effective bond wire inductance and reduce impedance in the ESD current path. This lowers voltage overshoot during fast transients (e.g., IEC 61000-4-2 0.7 ns rise time) and improves clamping consistency across temperature and process variation.
Is PESD2ETH-AD compatible with lead-free reflow soldering processes?
Yes. The SOT457 package is qualified for standard lead-free reflow profiles per J-STD-020, with peak temperature tolerance up to 260 °C. Recommended footprint dimensions and solder paste stencil openings are provided in Figures 11 and 12 of the datasheet.
PESD2ETH-AD/DG/B2X Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SC-74, SOT-457
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 12.3V (Typ)
- Current - Peak Pulse (10/1000µs):
- 3.5A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- USB
- Capacitance @ Frequency:
- 22pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSOP
PESD2ETH-AD/DG/B2X FAQ
1.How can I place an order for PESD2ETH-AD/DG/B2X through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD2ETH-AD/DG/B2X on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD2ETH-AD/DG/B2X reliable?
The price and inventory of PESD2ETH-AD/DG/B2X are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD2ETH-AD/DG/B2X is usually 5 days.
3.What payment methods are accepted for PESD2ETH-AD/DG/B2X?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD2ETH-AD/DG/B2X transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD2ETH-AD/DG/B2X?
PESD2ETH-AD/DG/B2X orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD2ETH-AD/DG/B2X order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD2ETH-AD/DG/B2X?
For technical support, including PESD2ETH-AD/DG/B2X datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD2ETH-AD/DG/B2X requirements.
6.How does Aetrix verify that PESD2ETH-AD/DG/B2X is sourced from the original manufacturer or authorized distributors?
All PESD2ETH-AD/DG/B2X products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD2ETH-AD/DG/B2X meets industry standards.
7.What is the process for return or replacement of PESD2ETH-AD/DG/B2X?
All PESD2ETH-AD/DG/B2X units undergo pre-shipment inspection (PSI). If there is an issue with PESD2ETH-AD/DG/B2X, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD2ETH-AD/DG/B2X part is unused and in its original packaging.
Return procedure for PESD2ETH-AD/DG/B2X:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD2ETH-AD/DG/B2X Tags

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