Nexperia USA Inc. PESD2ETH-ADX

Overview

PESD2ETH-AD from Nexperia is an ultra-low-capacitance double rail-to-rail ESD protection diode in SOT457 (TSOP6) package, designed to protect two high-speed automotive Ethernet data lines (e.g., 100BASE-T1) against ±12 kV IEC61000-4-2 and ±23 kV ISO 10605 transients. It integrates three ESD protection diodes - two rail-to-rail I/O paths plus one V_CC-to-ground path - enabling robust clamping even with no supply voltage applied.

For engineers reviewing the PESD2ETH-AD datasheet, PESD2ETH-AD pinout, PESD2ETH-AD application, or PESD2ETH-AD equivalent, key selection criteria include sub-2.3 pF per-channel capacitance at 1 MHz, 5.5 V reverse standoff voltage, AEC-Q101 qualification, and validated performance in 100BASE-T1 BroadR-Reach PHY interfaces with TJA1100 transceivers.

Technical Context

This device implements a triple-diode architecture: two symmetrical bidirectional rail-to-rail clamps (pins 1/6 ↔ 4/3) for differential signal lines, and one unidirectional Zener clamp (pin 5 → GND) for V_CC line protection. All clamps operate without bias dependency, ensuring protection during power-down states.

Clamping is characterized by low dynamic resistance (0.83 Ω positive, 0.62 Ω negative), fast response to ESD pulses (IEC61000-4-2 30 ns rise time), and stable 12.3 V clamping voltage at 3.5 A peak pulse current (8/20 µs waveform). Capacitance is measured separately per channel: 20 pF (I/O-to-GND via pin 5) and 2–2.3 pF (I/O-to-GND via pins 4/6).

Key Specifications

Pinout & Package

SOT457 (TSOP6) surface-mount plastic package: 1.1 mm × 2.7 mm × 1.0 mm body, 0.95 mm lead pitch, gull-wing leads. Designed for reflow soldering with defined footprint (3.45 mm × 1.95 mm land pattern) and wave-solder compatibility.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ESD protection applications.

Compared with NUP4105MR6T1G and ESD204-B1-W02, PESD2ETH-AD uniquely combines AEC-Q101 qualification, dual differential-channel rail-to-rail clamping, integrated V_CC protection, and 2.3 pF capacitance - making it the only drop-in solution validated for 100BASE-T1 PHY front-end protection per OPEN Alliance TC8 test plan.

Availability

PESD2ETH-AD is available at Aetrix Electronics and suitable for automotive Ethernet PHY interfaces, LVDS display interconnects, and USB 2.0 diagnostic ports requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PESD2ETH-AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in ESD protection, MOSFETs, and analog portfolio for automotive and industrial markets.

PESD2ETH-AD belongs to Nexperia's automotive-grade ESD protection product line, engineered specifically for high-speed differential data buses in vehicles - emphasizing ultra-low capacitance, AEC-Q101 compliance, and rail-to-rail clamping architecture.

FAQ

What is the recommended PCB layout for optimal ESD suppression with PESD2ETH-AD?

Place the device within 3 mm of the connector, route protected traces directly to its pins with minimum loop area, use a solid ground plane beneath the device, and avoid vias or stubs on I/O lines. The ground pin (Pin 2) must connect to ground plane via ≥2 thermal vias; V_CC (Pin 5) requires local 100 nF ceramic decoupling.

Does PESD2ETH-AD require external bias to protect signal lines during power-off conditions?

No. Its rail-to-rail diode architecture provides bidirectional clamping between I/O pins and both V_CC and GND without external bias. The V_CC pin functions as a clamping reference even at 0 V, enabling protection during system power-down or brownout events.

How does the 20 pF capacitance (Pin 5 to GND) impact circuit design?

That 20 pF value applies only to the V_CC-to-GND Zener path and does not load signal lines. Signal path capacitance remains 2–2.3 pF (Pins 1/3/4/6 to GND), so V_CC decoupling design must accommodate the additional 20 pF to ground - typically addressed by using ≥100 nF ceramic capacitors near the device.

Can PESD2ETH-AD be used for non-automotive 100BASE-T1 applications such as industrial Ethernet?

Yes. Its electrical specifications (5.5 V V_RWM, ±12 kV IEC61000-4-2, 2.3 pF) meet IEEE 802.3bw requirements for 100BASE-T1. However, AEC-Q101 qualification ensures superior thermal and mechanical robustness - beneficial in harsh industrial environments, though not strictly required for non-automotive use.