My Inquiry
My Account
Nexperia USA Inc. PESD2ETH-AXR
- Part No.:
- PESD2ETH-AXR
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- TO-253-4, TO-253AA
- Datasheet:
-
PESD2ETH-AXR.pdf
- Description:
- TVS DIODE 5.5VWM SOT143B
- Quantity:
- Payment:
- Shipping:
Inventory:6,719
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PESD2ETH-AX from Nexperia is an ultra-low-capacitance double rail-to-rail ESD protection diode in SOT143B package, designed to protect two high-speed automotive Ethernet (100BASE-T1) signal lines. It delivers 1.8 pF per channel capacitance, 5.5 V reverse standoff voltage, and AEC-Q101 qualification for under-hood deployment.
For engineers reviewing the PESD2ETH-AX datasheet, PESD2ETH-AX pinout, PESD2ETH-AX application, or PESD2ETH-AX equivalent, this device is selected for low-capacitance, rail-to-rail clamping in automotive differential data interfaces where signal integrity and ESD robustness up to ±12 kV (IEC 61000-4-2) are critical.
Technical Context
The PESD2ETH-AX integrates three ESD protection diodes: two rail-to-rail channels (pins 2–4 and 3–4) for bidirectional signal line protection, plus a dedicated ground-referenced Zener (pin 4–1) enabling protection even with no supply applied. Its architecture supports unpowered fail-safe operation in automotive PHY interfaces.
Clamping performance is characterized by +8 kV IEC 61000-4-2 pulses clamped to 27 V at 30 ns and −8 kV pulses clamped to −2.4 V, with <100 nA reverse leakage at 3 V and 0.7 V forward voltage at 1 mA - ensuring minimal loading on LVDS and BroadR-Reach signaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Diode Capacitance (per channel) | 1.8 pF at 1 MHz, 0 V reverse bias - preserves signal integrity on 100 Mbps+ differential buses |
| Reverse Standoff Voltage | 5.5 V - compatible with 3.3 V and 5 V automotive PHY supply domains |
| ESD Withstand (IEC 61000-4-2) | ±12 kV contact discharge - meets automotive EMC immunity requirements |
| ESD Withstand (ISO 10605) | ±15 kV (330 pF, 2 kΩ) - exceeds OPEN Alliance 100BASE-T1 specification |
| Clamping Voltage (VCL) | +27 V / −2.4 V at 30 ns for ±8 kV pulse - limits transient overvoltage to safe levels for PHY ICs |
| Reverse Leakage Current | 100 nA max at VR = 3 V - avoids DC loading of high-impedance receiver inputs |
| AEC-Q101 Qualified | Qualified per stress test standard for discrete semiconductors - validated for automotive temperature range (−40 °C to +125 °C) |
Pinout & Package
SOT143B plastic surface-mounted package (4-lead), 2.8 mm × 1.9 mm footprint, 0.95 mm height, with gull-wing leads optimized for reflow soldering per IPC-7095 guidelines.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Low-inductance return path for ESD current; connects to PCB ground plane |
| 2 | I/O 1 | Protected input/output for first differential pair leg (e.g., TDN) |
| 3 | I/O 2 | Protected input/output for second differential pair leg (e.g., TDP) |
| 4 | VCC | Supply reference for rail-to-rail clamping; enables protection without external bias |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail bidirectional clamping | Enables symmetric protection of both signal polarities without polarity constraints on differential lines |
| Ultra-low 1.8 pF channel capacitance | Minimizes signal distortion and insertion loss on 66.67 MHz 100BASE-T1 waveforms |
| Three-diode topology (2× rail-to-rail + 1× Zener) | Guarantees protection during power-down or supply fault conditions via pin 4–1 path |
| AEC-Q101 qualification | Validated for automotive under-hood environments including thermal cycling, humidity, and mechanical shock |
| Small SOT143B footprint | Reduces PCB real estate and parasitic inductance - critical for ESD layout best practices |
Applications
| 100BASE-T1 Automotive Ethernet | LVDS Automotive Interface |
|---|---|
Use Scenario: Protection of differential pairs between TJA1100 PHY and RJ45 connector in ADAS domain controllers. IC Role / Device Role: Primary ESD clamp placed within 3 mm of connector per layout guideline, shunting transients to VCC and GND. Use Value: Maintains <1.5% signal rise-time degradation while surviving ±15 kV ISO 10605 pulses. | Use Scenario: Shielding camera sensor output lines (e.g., MAX96705 serializer interface) in rear-view systems. IC Role / Device Role: Low-capacitance guard on LVDS clock and data lanes to prevent latch-up during assembly ESD events. Use Value: Enables >1 Gbps data throughput with <0.1 dB insertion loss at 1 GHz due to 1.8 pF loading. |
| USB 2.0 Automotive | Automotive Infotainment Display Link |
Use Scenario: Protecting USB 2.0 D+/D− lines connecting head unit to telematics control unit (TCU). IC Role / Device Role: Dual-channel ESD suppressor mounted adjacent to USB receptacle, referenced to system VBUS and GND. Use Value: Prevents PHY damage from hot-plug ESD while maintaining full-speed (480 Mbps) eye diagram compliance. | Use Scenario: Securing MIPI D-PHY or FPD-Link III video bus between infotainment processor and TFT display module. IC Role / Device Role: Signal-line protector on high-frequency clock and data lanes exposed to dashboard ESD risk zones. Use Value: Delivers sub-2 pF loading to avoid jitter accumulation and pixel corruption in 1080p@60 Hz video streams. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD56201D-2/TR | 1.5 pF capacitance, 5.5 V VRWM, ±20 kV IEC 61000-4-2, SOD-323 package | Higher ESD rating but larger package; lacks rail-to-rail topology and VCC-referenced third diode | Select when maximum ESD margin is prioritized over board space and unpowered protection capability |
| TPD2E001DRYR | 1.0 pF capacitance, 5.5 V VRWM, ±15 kV IEC 61000-4-2, SOT-553 package | Lower capacitance but only dual-diode configuration; no VCC terminal or third diode for supply-independent clamping | Select for non-automotive USB/LVDS where ultra-low capacitance outweighs fail-safe unpowered operation |
Compared with ESD56201D-2/TR and TPD2E001DRYR, the PESD2ETH-AX uniquely combines rail-to-rail clamping, a third Zener diode for zero-supply protection, AEC-Q101 qualification, and SOT143B's compact 2.8 mm × 1.9 mm footprint - making it the only solution qualified for 100BASE-T1 automotive Ethernet PHY protection per OPEN Alliance requirements.
Availability
PESD2ETH-AX is available at Aetrix Electronics and suitable for automotive Ethernet PHY protection, LVDS camera links, and USB 2.0 in-vehicle connectivity requiring stable component supply across extended temperature and lifecycle demands.
Supply support for PESD2ETH-AX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency-enhancing components - delivering high-performance, reliable, and scalable solutions for automotive, industrial, and consumer markets.
The PESD2ETH-AX belongs to Nexperia's automotive-grade ESD protection portfolio, engineered specifically for high-speed differential data interfaces in vehicles, with emphasis on 100BASE-T1 compliance, low capacitance, and fail-safe operation.
FAQ
What is the purpose of the VCC pin (Pin 4) in the PESD2ETH-AX?
Pin 4 (VCC) serves as the positive rail reference for the two rail-to-rail diodes (between Pins 2–4 and 3–4), enabling symmetrical clamping above and below the supply level. It also connects to a third Zener diode (Pin 4–1), allowing ESD protection to function even when the system supply is off - a critical feature for automotive wake-up and fail-safe scenarios.
Can PESD2ETH-AX be used on single-ended signals like CAN or LIN?
No - the PESD2ETH-AX is optimized for differential high-speed data lines (e.g., 100BASE-T1, LVDS, USB 2.0) and lacks the asymmetric clamping architecture required for single-ended buses. Its rail-to-rail topology and 1.8 pF per-channel capacitance are tuned for balanced signaling; using it on CAN or LIN would result in improper clamping thresholds and potential signal distortion.
How does the 1.8 pF diode capacitance impact 100BASE-T1 signal integrity?
At 100BASE-T1's 66.67 MHz fundamental frequency and harmonics up to 300 MHz, 1.8 pF adds negligible capacitive loading (<0.2% impedance reduction at 100 MHz), preserving rise/fall times and eye opening. Measured data confirms <1.5% rise-time degradation and full compliance with OPEN Alliance emission and immunity masks when placed per layout guidelines.
Is the SOT143B package suitable for automated optical inspection (AOI) after reflow?
Yes - the SOT143B's gull-wing lead geometry, defined solder land dimensions (0.7 mm × 0.9 mm per pad), and 0.65 mm pitch enable reliable AOI detection of solder bridging, insufficient wetting, and lateral misalignment. Nexperia provides IPC-7351-compliant footprint data and recommends 50–75 µm stencil aperture reduction for optimal paste release and void control.
PESD2ETH-AXR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- TO-253-4, TO-253AA
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- Ethernet
- Capacitance @ Frequency:
- 16pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-143B
PESD2ETH-AXR FAQ
1.How can I place an order for PESD2ETH-AXR through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD2ETH-AXR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD2ETH-AXR reliable?
The price and inventory of PESD2ETH-AXR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD2ETH-AXR is usually 5 days.
3.What payment methods are accepted for PESD2ETH-AXR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD2ETH-AXR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD2ETH-AXR?
PESD2ETH-AXR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD2ETH-AXR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD2ETH-AXR?
For technical support, including PESD2ETH-AXR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD2ETH-AXR requirements.
6.How does Aetrix verify that PESD2ETH-AXR is sourced from the original manufacturer or authorized distributors?
All PESD2ETH-AXR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD2ETH-AXR meets industry standards.
7.What is the process for return or replacement of PESD2ETH-AXR?
All PESD2ETH-AXR units undergo pre-shipment inspection (PSI). If there is an issue with PESD2ETH-AXR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD2ETH-AXR part is unused and in its original packaging.
Return procedure for PESD2ETH-AXR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD2ETH-AXR Tags
-
ESD9B5.0ST5G
onsemi
-
DESD3V3E1BL-7B
Diodes Incorporated
-
ESD5Z3.3T1G
onsemi
-
D5V0H1B2LP-7B
Diodes Incorporated
-
D5V0P1B2LP-7B
Diodes Incorporated
-
DESD5V0U1BA-7
Diodes Incorporated
-
ESD5Z5.0T1G
onsemi
-
DESD5V0U1BB-7
Diodes Incorporated
-
D12V0L1B2LP-7B
Diodes Incorporated
-
PESD2V0Y1BSFYL
Nexperia USA Inc.
-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage
-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
