My Inquiry
My Account
Nexperia USA Inc. PESD2ETH-DX
- Part No.:
- PESD2ETH-DX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SC-74, SOT-457
- Datasheet:
-
PESD2ETH-DX.pdf
- Description:
- TVS DIODE 5.5VWM 11.8VC 6TSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,872
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PESD2ETH-D from Nexperia is an ultra-low-capacitance double rail-to-rail ESD protection diode in SOT457 (TSOP6) package, designed to protect two high-speed automotive Ethernet data lines (e.g., 100BASE-T1) against ±8 kV IEC 61000-4-2 ESD events. It integrates three ESD protection diodes - two rail-to-rail I/O paths and one VCC-to-ground path - enabling robust clamping (VCL = 11.8 V at 2.5 A) with only 1.3 pF capacitance per channel and AEC-Q101 qualification.
For engineers reviewing the PESD2ETH-D datasheet, PESD2ETH-D pinout, PESD2ETH-D application, or PESD2ETH-D equivalent, this device is selected for low-distortion, high-frequency signal line protection where sub-2 pF capacitance, <5.5 V reverse standoff voltage, and guaranteed operation across –55 °C to +150 °C ambient are critical in automotive Ethernet and LVDS interfaces.
Technical Context
The PESD2ETH-D implements a triple-diode architecture: two symmetrical rail-to-rail bidirectional diodes (pins 1–2 and 3–2, plus pins 4–2 and 6–2) provide differential ESD clamping on two independent high-speed channels, while a third Zener diode (pin 5–2) protects the VCC rail even under unpowered conditions. Its dynamic resistance is 1.1 Ω (positive clamping) and 0.9 Ω (negative clamping), ensuring fast transient response without signal degradation.
It operates within a 5.5 V reverse standoff voltage (VRWM) and delivers 11.8 V clamping voltage (VCL) at 2.5 A 8/20 µs pulse, with leakage current ≤100 nA at 5.5 V and forward voltage of 0.7 V at 1 mA - all verified per IEC 61000-4-2 and AEC-Q101 stress test requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VRWM | 5.5 V maximum reverse standoff voltage - ensures no conduction during normal 5 V system operation. |
| Cd (per channel) | 1.3 pF typical capacitance at 0 V bias - preserves signal integrity up to >1 GHz in 100BASE-T1 and LVDS links. |
| VCL | 11.8 V clamping voltage at 2.5 A 8/20 µs pulse - limits transient overvoltage to safe levels for PHY ICs. |
| IPPM | 2.5 A rated peak pulse current - withstands automotive-level surge transients without failure. |
| VESD | ±8 kV contact discharge per IEC 61000-4-2 - meets automotive ESD immunity requirements. |
| Tamb | –55 °C to +150 °C operating ambient range - supports under-hood and ADAS module deployment. |
| AEC-Q101 | Qualified for automotive discrete semiconductors - validated for reliability in harsh automotive environments. |
Pinout & Package
SOT457 (TSOP6) plastic surface-mounted package: 1.1 mm × 2.7 mm × 1.0 mm body, 0.95 mm lead pitch, 6-terminal lead frame with gull-wing leads. Compatible with standard reflow and wave soldering per IPC-7351B.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O 1 (anode/cathode pair) | First protected high-speed data line terminal - bidirectionally clamped between pin 1 and GND (pin 2). |
| 2 | GND | Common reference and ESD return path - must be connected to low-inductance chassis ground. |
| 3 | I/O 2 (anode/cathode pair) | Second protected high-speed data line terminal - forms differential pair with pin 4 or 6. |
| 4 | I/O 2 (redundant path) | Alternate I/O 2 terminal - enables flexible PCB routing for differential signal pairs in TSOP6 layout. |
| 5 | VCC | Supply rail protection node - connects internal Zener diode to clamp VCC transients even when unpowered. |
| 6 | I/O 1 (redundant path) | Alternate I/O 1 terminal - supports symmetric layout of differential signals with minimal trace length asymmetry. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail bidirectional clamping | Enables protection of both positive and negative transients on high-speed differential lines without DC bias dependency. |
| 1.3 pF channel capacitance | Minimizes insertion loss and phase distortion in 100BASE-T1 (66.67 MHz fundamental, harmonics to 1 GHz). |
| VCC-to-GND Zener diode | Provides fail-safe ESD protection on power rail even when system is powered down or disconnected. |
| AEC-Q101 qualification | Validated for temperature cycling, HTRB, UHAST, and mechanical shock - required for automotive Tier-1 supply chain compliance. |
| 2.5 A peak pulse rating | Supports IEC 61000-4-5 Level 3 surge immunity (1 kV line-to-earth) when combined with common-mode chokes. |
Applications
| 100BASE-T1 Automotive Ethernet | Automotive LVDS Interfaces |
|---|---|
Use Scenario: Protection of differential pair in TJA1100-based 100BASE-T1 PHY modules on vehicle domain controllers. IC Role / Device Role / Timing Role: ESD transient suppressor placed directly at RJ45 connector entry point, before common-mode choke. Use Value: 1.3 pF capacitance prevents signal rise-time degradation (<1 ns), maintaining eye diagram compliance per OPEN Alliance spec. |
Use Scenario: Shielded cable interface between camera sensor and ADAS processor in rear-view or surround-view systems. IC Role / Device Role / Timing Role: Bidirectional rail-to-rail clamp on LVDS clock/data pairs operating at 155.52 MHz. Use Value: Clamping voltage ≤11.8 V ensures receiver input stays within absolute maximum ratings during ±8 kV ESD events. |
| USB 2.0 Automotive | Automotive Infotainment Display Links |
Use Scenario: ESD protection on USB 2.0 D+/D− lines in head-unit or telematics control units exposed to user-accessible ports. IC Role / Device Role / Timing Role: Low-capacitance shunt protector placed adjacent to USB receptacle, referenced to system ground. Use Value: Sub-2 pF loading avoids USB 2.0 eye diagram mask violations at 480 Mbps full-speed signaling. |
Use Scenario: High-resolution display interface (e.g., MIPI D-PHY or FPD-Link III) between infotainment SoC and TFT panel. IC Role / Device Role / Timing Role: Dual-channel ESD guard on differential pixel clock and data lanes in display timing-critical path. Use Value: Matched 1.3 pF capacitance per channel maintains skew <5 ps between lanes, preserving pixel alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor NUP4201MR6T1G | Higher 3.5 pF capacitance per channel; single-rail architecture; no dedicated VCC clamp diode. | Limited to non-automotive LVDS or USB; not AEC-Q101 qualified. | Select only for cost-sensitive industrial designs where <2 pF is not required. |
| Vishay VEML6030X01 | Optical sensor IC - not an ESD diode; functionally incompatible. | N/A - incorrect device category. | Not a valid alternative; excluded from ESD protection selection. |
Compared with NUP4201MR6T1G, PESD2ETH-D delivers 63% lower capacitance and integrated VCC clamping for fail-safe operation, making it uniquely suitable for automotive Ethernet PHY protection where signal fidelity and unpowered robustness are mandatory.
Availability
PESD2ETH-D is available at Aetrix Electronics and suitable for automotive Ethernet PHY modules, ADAS camera links, and infotainment display interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for PESD2ETH-D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors - including ESD protection, logic, MOSFETs, and bipolar transistors - serving automotive, industrial, and consumer markets.
The PESD2ETH-D belongs to Nexperia's automotive-grade ESD protection portfolio, engineered specifically for high-speed serial interfaces in vehicles where AEC-Q101 compliance, ultra-low capacitance, and rail-to-rail clamping are non-negotiable.
FAQ
What is the maximum clamping voltage of PESD2ETH-D during an ESD event?
The PESD2ETH-D delivers a typical clamping voltage (VCL) of 11.8 V at 2.5 A peak pulse current (8/20 µs waveform), measured from I/O pins to GND. This value is confirmed per IEC 61000-4-2 testing and ensures downstream PHY ICs remain within their absolute maximum input voltage ratings during ±8 kV contact discharge events.
Can PESD2ETH-D protect signal lines when the system is unpowered?
Yes. The device includes a dedicated Zener diode between pin 5 (VCC) and pin 2 (GND), enabling clamping of transients on the supply rail even when VCC is at 0 V. This fail-safe behavior ensures protection remains active during power-down, hot-swap, or battery-disconnect scenarios common in automotive modules.
Is PESD2ETH-D compatible with automated optical inspection (AOI) after reflow?
Yes. The SOT457 package has gull-wing leads with 0.95 mm pitch and defined solder land geometry (per Fig. 11 in the datasheet), supporting reliable AOI detection of solder joint quality, coplanarity, and bridging. Its marking code "L8" is laser-etched and legible under standard AOI lighting and magnification.
How does the dual I/O pin configuration (pins 1/6 and 3/4) improve layout flexibility?
Pins 1 and 6 both serve as I/O 1 terminals, while pins 3 and 4 both serve as I/O 2 terminals - allowing symmetric routing of differential pairs without trace length mismatch. This redundancy reduces PCB layer count and improves impedance matching in tight-space automotive modules, directly supporting 100BASE-T1's strict <0.1 mm length-matching requirement.
PESD2ETH-DX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SC-74, SOT-457
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 11.8V (Typ)
- Current - Peak Pulse (10/1000µs):
- 2.5A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- -
- Capacitance @ Frequency:
- 16pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSOP
PESD2ETH-DX FAQ
1.How can I place an order for PESD2ETH-DX through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD2ETH-DX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD2ETH-DX reliable?
The price and inventory of PESD2ETH-DX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD2ETH-DX is usually 5 days.
3.What payment methods are accepted for PESD2ETH-DX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD2ETH-DX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD2ETH-DX?
PESD2ETH-DX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD2ETH-DX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD2ETH-DX?
For technical support, including PESD2ETH-DX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD2ETH-DX requirements.
6.How does Aetrix verify that PESD2ETH-DX is sourced from the original manufacturer or authorized distributors?
All PESD2ETH-DX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD2ETH-DX meets industry standards.
7.What is the process for return or replacement of PESD2ETH-DX?
All PESD2ETH-DX units undergo pre-shipment inspection (PSI). If there is an issue with PESD2ETH-DX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD2ETH-DX part is unused and in its original packaging.
Return procedure for PESD2ETH-DX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD2ETH-DX Tags
-
ESD9B5.0ST5G
onsemi
-
DESD3V3E1BL-7B
Diodes Incorporated
-
ESD5Z3.3T1G
onsemi
-
D5V0H1B2LP-7B
Diodes Incorporated
-
D5V0P1B2LP-7B
Diodes Incorporated
-
DESD5V0U1BA-7
Diodes Incorporated
-
ESD5Z5.0T1G
onsemi
-
DESD5V0U1BB-7
Diodes Incorporated
-
D12V0L1B2LP-7B
Diodes Incorporated
-
PESD2V0Y1BSFYL
Nexperia USA Inc.
-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage
-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
