Nexperia USA Inc. PESD3USB3B/CX
- Part No.:
- PESD3USB3B/CX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- 15-UFBGA, WLCSP
- Datasheet:
-
PESD3USB3B/CX.pdf
- Description:
- TVS DIODE 4VWM 3.7VC DSN0603-2
- Quantity:
- Payment:

- Shipping:

Inventory:5,474
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Product details
Overview
PESD3USB3B/C from Nexperia is a triple-channel bidirectional ESD protection diode array for high-speed differential data lines, featuring ±20 kV IEC 61000-4-2 contact discharge rating, 0.29 pF typical diode capacitance per line, and 16.1 GHz f-3dB cut-off frequency - deployed in USB 3.2, HDMI 2.0, and MIPI D-PHY interfaces on mobile and display subsystems.
For engineers reviewing the PESD3USB3B/C datasheet, PESD3USB3B/C pinout, PESD3USB3B/C application, or PESD3USB3B/C equivalent, this device delivers ultra-low-capacitance transient protection with footprint compatibility to PCMFxUSB3B/C common-mode filters, enabling drop-in layout reuse across ESD-only and combined ESD+CMF designs.
Technical Context
The PESD3USB3B/C integrates three independent, matched differential channel pairs using TrEOS process technology, each with snap-back clamping behavior that reduces dynamic resistance to 0.2 Ω during TLP stress (100 ns), achieving low clamping voltage under ±20 kV ESD events. Its symmetrical WLCSP15 layout preserves differential impedance integrity.
Designed specifically for >5 Gbps serial links, it maintains <0.5 dB insertion loss up to 8 GHz and supports clean 10 Gbps USB 3.2 eye diagrams when placed at Type-C connector ingress. Ground pins B1–B3 are isolated from internal circuitry, minimizing ground bounce coupling between channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±20 kV contact discharge (IEC 61000-4-2); protects SoC PHY inputs from system-level ESD without latch-up. |
| Diode Capacitance | 0.29 pF per line at 1 MHz/2.5 V; enables minimal signal distortion on 10 Gbps USB 3.2 and 6 Gbps HDMI 2.0 links. |
| f-3dB Cut-off | 16.1 GHz differential mode; ensures full bandwidth preservation for SuperSpeed+ and TMDS signaling. |
| Dynamic Resistance | 0.2 Ω (TLP, 100 ns); sustains low clamping voltage (<8 V) during fast-rising ESD transients. |
| Breakdown Voltage | 6–9 V (IR = 1 mA); safely isolates protected lines from DC bias while triggering before PHY damage thresholds. |
| Leakage Current | 1–100 nA per line at 5 V; avoids DC loading of high-impedance receiver inputs. |
Pinout & Package
Package: WLCSP15 (6-3-6 bump configuration), 2.42 mm × 1.22 mm × 0.64 mm body, 0.4 mm pitch, solder bumps compatible with standard 0.1 mm stencil thickness.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1, A3, A5 | CH1_IN+, CH2_IN+, CH3_IN+ | External-side positive terminals for each differential pair; connect directly to connector-side traces. |
| A2, A4, A6 | CH1_IN−, CH2_IN−, CH3_IN− | External-side negative terminals; maintain strict length matching with corresponding A1/A3/A5 pins. |
| B1, B2, B3 | GND_CH1, GND_CH2, GND_CH3 | Isolated ground terminals - no internal connection; used for local PCB ground stitching only. |
| C1, C3, C5 | CH1_OUT+, CH2_OUT+, CH3_OUT+ | Internal-side positive terminals; route to SoC PHY differential inputs with controlled impedance. |
| C2, C4, C6 | CH1_OUT−, CH2_OUT−, CH3_OUT− | Internal-side negative terminals; mirror C1/C3/C5 for balanced routing and return path control. |
Key Features
| Feature | Design Value |
|---|---|
| Footprint compatibility | Matches PCMFxUSB3B/C common-mode filters - enables single PCB land pattern for ESD-only or ESD+CMF variants. |
| TrEOS protection process | Delivers superior system-level robustness by reducing snap-back clamping voltage below 8 V at 9.5 A peak pulse. |
| Ultra-low capacitance | 0.29 pF per line minimizes signal attenuation and jitter accumulation on 10 Gbps differential lanes. |
| Triple-channel integration | Single WLCSP15 package protects three independent differential pairs - reduces board area vs. discrete solutions. |
| Differential impedance stability | TDR shows Zdif ≈ 90 Ω across 0–10 GHz; preserves link integrity without external tuning components. |
Applications
| USB 3.2 Gen 2 Interface | HDMI 2.0 Source Port |
|---|---|
Use Scenario: Protecting SuperSpeed TX/RX differential pairs at the USB Type-C receptacle on a laptop motherboard. IC Role / Device Role / Timing Role: Bidirectional ESD clamp placed between connector and SoC PHY; no timing function - purely signal integrity safeguard. Use Value: Maintains 10 Gbps eye opening (Fig. 4/5) while surviving ±20 kV contact discharge without degrading insertion loss (<0.3 dB @ 5 GHz). |
Use Scenario: Shielding TMDS clock and data channels on an HDMI 2.0 source port of a streaming stick. IC Role / Device Role / Timing Role: Passive ESD shunt on all three TMDS differential pairs; zero propagation delay or skew impact. Use Value: Enables clean 6 Gbps eye diagrams (Fig. 8/9) with <0.29 pF loading - critical for pixel-perfect 4K@60Hz video transmission. |
| MIPI D-PHY CSI-2 Camera Link | Mobile Display Serial Interface |
Use Scenario: ESD protection on dual-lane MIPI D-PHY CSI-2 interface between image sensor and application processor in smartphone. IC Role / Device Role / Timing Role: Low-capacitance transient suppressor on high-speed data lanes; no effect on lane calibration or LP/HS switching timing. Use Value: Prevents ESD-induced pixel corruption or frame drops by clamping transients before PHY input damage threshold (≤6 V). |
Use Scenario: Protecting DSI differential pairs on a tablet's display module flex cable connector. IC Role / Device Role / Timing Role: Symmetric ESD clamp on each DSI data lane; preserves differential skew budget (<1 ps) due to matched internal paths. Use Value: Eliminates display artifacts (e.g., vertical stripes) caused by ESD on high-resolution OLED panels operating at 2.5 Gbps per lane. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar differential-line ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PCMF3USB3B/C | Integrates common-mode filter + ESD protection; higher insertion loss (−1.2 dB @ 5 GHz) and 0.45 pF capacitance. | Required where EMI filtering is needed alongside ESD; not suitable if only transient suppression is required. | Select when board space allows combined filtering and ESD, and system-level EMC testing reveals CM noise issues. |
| TPD2EUSB30DR | Single-channel, SOT-563 package; 0.5 pF capacitance; ±12 kV ESD rating; lower bandwidth (f-3dB = 3.5 GHz). | Suitable for lower-speed USB 2.0 or legacy MIPI; not rated for 10 Gbps operation or HDMI 2.0. | Choose only for cost-sensitive, non-SuperSpeed designs where 0.5 pF loading and reduced ESD margin are acceptable. |
Compared with PCMF3USB3B/C, PESD3USB3B/C offers lower capacitance and higher bandwidth but no common-mode rejection; versus TPD2EUSB30DR, it delivers triple-channel integration, 67% lower capacitance, and 4.6× higher ESD rating - making it the sole fit for 10 Gbps USB 3.2 and 6 Gbps HDMI 2.0 systems.
Availability
PESD3USB3B/C is available at Aetrix Electronics and suitable for USB 3.2 host ports, HDMI 2.0 source interfaces, and MIPI D-PHY camera modules requiring stable component supply across high-volume mobile and display production programs.
Supply support for PESD3USB3B/C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-performance, energy-efficient logic, analog, and MOSFET devices, serving automotive, industrial, and consumer markets with scalable manufacturing and rigorous quality systems.
The PESDxUSB3B/C series belongs to Nexperia's TrEOS ESD protection portfolio, engineered specifically for ultra-high-speed differential interfaces where sub-0.3 pF loading and ±20 kV system-level robustness are mandatory design requirements.
FAQ
What is the maximum data rate supported by PESD3USB3B/C?
PESD3USB3B/C supports up to 10 Gbps differential signaling, validated via USB 3.2 eye diagrams (Fig. 4/6) and 16.1 GHz f-3dB cut-off. Its 0.29 pF capacitance and 90 Ω differential impedance ensure minimal jitter and insertion loss at SuperSpeed+ rates - no derating required for Gen 2 operation.
Can PESD3USB3B/C be used with HDMI 2.0 without signal degradation?
Yes - Nexperia's test data (Fig. 8–11) confirms clean 6 Gbps HDMI 2.0 eye diagrams with PESD3USB3B/C installed. Its 0.29 pF per line capacitance and flat insertion loss (<0.5 dB up to 8 GHz) prevent TMDS timing skew or amplitude loss, meeting HDMI 2.0 compliance margins.
Are the B1–B3 pins internally connected?
No - B1, B2, and B3 are isolated ground terminals with no internal connection to the ESD diodes or silicon die. They serve solely for mechanical anchoring and local PCB ground stitching near the WLCSP15 package; connecting them to system ground improves thermal dissipation and EMI shielding.
How does PESD3USB3B/C differ from PCMF3USB3B/C in layout implementation?
PESD3USB3B/C uses identical WLCSP15 footprint and bump pattern as PCMF3USB3B/C (per Table 1 and Fig. 21), allowing direct PCB land pattern reuse. The key difference is functional: PESD3USB3B/C provides ESD-only protection, while PCMF3USB3B/C adds integrated common-mode filtering - requiring no layout change when upgrading from ESD-only to combined ESD+CMF.
PESD3USB3B/CX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- 15-UFBGA, WLCSP
- Series:
- PESDxUSB3B/C
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 4V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- 9.5A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- HDMI, USB
- Capacitance @ Frequency:
- 0.29pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 15-WLCSP (2.37x1.17)
PESD3USB3B/CX FAQ
1.How can I place an order for PESD3USB3B/CX through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD3USB3B/CX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD3USB3B/CX reliable?
The price and inventory of PESD3USB3B/CX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD3USB3B/CX is usually 5 days.
3.What payment methods are accepted for PESD3USB3B/CX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD3USB3B/CX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD3USB3B/CX?
PESD3USB3B/CX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD3USB3B/CX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD3USB3B/CX?
For technical support, including PESD3USB3B/CX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD3USB3B/CX requirements.
6.How does Aetrix verify that PESD3USB3B/CX is sourced from the original manufacturer or authorized distributors?
All PESD3USB3B/CX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD3USB3B/CX meets industry standards.
7.What is the process for return or replacement of PESD3USB3B/CX?
All PESD3USB3B/CX units undergo pre-shipment inspection (PSI). If there is an issue with PESD3USB3B/CX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD3USB3B/CX part is unused and in its original packaging.
Return procedure for PESD3USB3B/CX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD3USB3B/CX Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

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Diodes Incorporated

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D5V0P1B2LP-7B
Diodes Incorporated

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DESD5V0U1BA-7
Diodes Incorporated

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ESD5Z5.0T1G
onsemi

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DESD5V0U1BB-7
Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
Nexperia USA Inc.

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DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

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D5V0L1B2WS-7
Diodes Incorporated
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