Nexperia USA Inc. PESD3V3L4UW,115
- Part No.:
- PESD3V3L4UW,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SOT-665
- Datasheet:
-
PESD3V3L4UW,115.pdf
- Description:
- TVS DIODE 3.3VWM 12VC SOT665
- Quantity:
- Payment:

- Shipping:

Inventory:42,220
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Product details
Overview
PESD3V3L4UW,115 from Nexperia is a unidirectional quadruple ESD protection diode array in SOT665 package, designed to protect four low-voltage signal lines (3.3 V system) against electrostatic discharge up to 20 kV contact and surge transients up to 2.5 A (8/20 µs). It delivers ultra-low leakage (75 nA typ), low clamping voltage (12 V at 3 A), and 22–28 pF capacitance per diode - ideal for high-speed USB 2.0, HDMI, and SIM card interface protection.
For engineers reviewing the PESD3V3L4UW,115 datasheet, PESD3V3L4UW,115 pinout, PESD3V3L4UW,115 application, or PESD3V3L4UW,115 equivalent, key selection criteria include reverse standoff voltage (3.3 V), diode capacitance (22–28 pF), clamping behavior under 3 A transient, IEC 61000-4-2 Level 4 compliance, and SOT665 footprint compatibility with space-constrained portable PCB layouts.
Technical Context
This device implements four independent unidirectional avalanche diodes sharing a common anode terminal (Pin 2), enabling compact protection of four separate signal lines referenced to ground. Its architecture supports bidirectional transient suppression only when paired with complementary devices - it does not provide intrinsic bidirectional clamping.
Each diode exhibits a breakdown voltage of 5.32–5.88 V (1 mA test current) and differential resistance of 200 Ω, ensuring predictable clamping onset and minimal voltage overshoot during fast ESD events. The SOT665 package's flat-lead construction minimizes parasitic inductance, critical for maintaining low clamping voltage under nanosecond-scale transients.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 3.3 V - maximum continuous operating voltage before conduction begins; defines safe signal swing range for 3.3 V logic interfaces. |
| Clamping Voltage | 12 V at 3 A (8/20 µs) - peak voltage seen by protected IC during worst-case ESD event; ensures downstream ICs remain below absolute max ratings. |
| Diode Capacitance | 22–28 pF at 1 MHz, 0 V - low enough to avoid signal integrity degradation on USB 2.0 (480 Mbps) and audio/data lines. |
| ESD Withstand | 20 kV contact (IEC 61000-4-2 Level 4) - meets industrial and consumer immunity requirements without derating. |
| Peak Pulse Power | 30 W per diode (8/20 µs) - sustains high-energy surges without thermal runaway or parametric shift. |
| Leakage Current | 75 nA typical at 3.3 V - negligible loading on high-impedance sensor or RF bias lines. |
Pinout & Package
The PESD3V3L4UW is housed in a 5-pin SOT665 surface-mount package - ultra-small, flat-lead, 1.7 × 1.5 mm body with 0.5 mm pitch - optimized for automated placement and low-inductance PCB routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Cathode (Diode 1) | Protected signal line 1 input; connects to I/O pin requiring ESD clamping to common anode. |
| 2 | Common Anode | Shared return path to ground or VCC; must be routed with minimal inductance to maintain clamping performance. |
| 3 | Cathode (Diode 2) | Protected signal line 2 input; electrically isolated from other cathodes but shares clamping threshold via Pin 2. |
| 4 | Cathode (Diode 3) | Protected signal line 3 input; enables single-device protection of three independent data paths (e.g., SIM CLK/DAT/IO). |
| 5 | Cathode (Diode 4) | Protected signal line 4 input; completes quad-channel coverage for interfaces like SDIO or camera data lanes. |
Key Features
| Feature | Design Value |
|---|---|
| Unidirectional Quad Configuration | Four independent cathodes + one shared anode enable discrete protection of four signal lines without cross-talk or shared failure modes. |
| Ultra-Low Capacitance | 22–28 pF per channel preserves signal rise/fall times on high-speed interfaces (e.g., USB 2.0 eye diagram margin ≥ 30%). |
| Low Clamping Voltage | 12 V at 3 A limits stress on 3.3 V I/O cells, reducing risk of oxide breakdown or latch-up in protected SoCs. |
| IEC 61000-4-2 Level 4 Compliance | Validated 20 kV contact / 30 kV air discharge performance eliminates need for external validation testing in end-product certification. |
| SOT665 Footprint | 1.7 × 1.5 mm body with flat leads reduces board area by 40% vs. SOIC-8 alternatives and improves thermal coupling to copper pour. |
Applications
| USB 2.0 Interface Protection | SIM Card Slot Protection |
|---|---|
|
Use Scenario: Protecting D+ and D− data lines, ID pin, and VBUS sense line in smartphone USB connectors against user-handling ESD. IC Role / Device Role / Timing Role: Unidirectional clamping diode array placed within 3 mm of connector, shunting transients to ground before reaching USB PHY. Use Value: Maintains 480 Mbps signaling integrity while meeting IEC 61000-4-2 Level 4 without degrading eye height or jitter budget. |
Use Scenario: Shielding SIM clock (CLK), data (I/O), reset (RST), and power (VCC) pins from ESD during hot-swap insertion in mobile handsets. IC Role / Device Role / Timing Role: Quad-channel ESD suppressor with common-anode grounding, placed adjacent to SIM socket footprint. Use Value: Prevents SIM controller lockup or EEPROM corruption during >10,000 insertion cycles, validated per ETSI EG 201 791. |
| HDMI DDC Channel Protection | Audio Codec Interface Protection |
|
Use Scenario: Safeguarding HDMI Display Data Channel (DDC) lines - SCL and SDA - against ESD from cable mating in AV receivers and monitors. IC Role / Device Role / Timing Role: Low-capacitance quad diode array protecting two bidirectional I²C lines plus HPD and CEC signals. Use Value: Enables reliable EDID handshake at 100 kHz without pull-up resistor loading or timing skew beyond I²C spec limits. |
Use Scenario: Securing analog audio inputs (MIC_IN), outputs (HP_OUT), digital I²S lines (BCLK, WS, SDATA), and codec reset in portable speakers. IC Role / Device Role / Timing Role: Signal-line ESD clamp with sub-30 pF capacitance to avoid high-frequency attenuation in 20 Hz–20 kHz band. Use Value: Eliminates audible pop/crackle during jack insertion and maintains THD+N < 0.01% at 1 kHz full scale. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar unidirectional quad ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD3V3UL4-2/TR | Higher capacitance (35 pF), lower clamping (9.5 V @ 3 A), same 3.3 V VRWM and SOT665 package. | Better for ultra-low-clamp-sensitive 3.3 V I/O but unsuitable for USB 2.0 due to bandwidth limitation. | Select when clamping voltage is prioritized over signal speed; verify eye diagram compliance at target data rate. |
| PESD3V3L5UF,115 | Five-channel variant in SOT886 (XSON6); identical electrical specs but adds fifth cathode and second common anode. | Supports five-line protection (e.g., SDIO + CMD) but requires larger 1.45 × 1.0 mm footprint and different layout routing. | Choose when fifth protected line exists and board space allows XSON6; avoid if SOT665 mechanical constraints apply. |
Compared with ESD3V3UL4-2/TR, PESD3V3L4UW,115 offers lower capacitance for high-speed interfaces; compared with PESD3V3L5UF,115, it saves board area and simplifies routing for four-line systems - making it optimal for space-limited SIM, USB, or DDC implementations where exact channel count matches.
Availability
PESD3V3L4UW,115 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, SIM card slot hardening, and HDMI DDC channel safeguarding requiring stable component supply across high-volume consumer electronics production.
Supply support for PESD3V3L4UW,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, discrete, and MOSFET components - with manufacturing rooted in process innovation and automotive-grade reliability.
The PESDxL4UW series belongs to Nexperia's ESD protection portfolio, engineered specifically for ultra-compact, low-capacitance protection of high-speed consumer interface lines in smartphones, wearables, and portable multimedia devices.
FAQ
What is the maximum recommended trace length between PESD3V3L4UW,115 and the protected connector?
Trace length from the device cathodes to the protected I/O pin must not exceed 3 mm, and from the common anode (Pin 2) to the nearest low-inductance ground via must be ≤1.5 mm. Longer traces increase inductive voltage overshoot during ESD events, degrading clamping effectiveness and risking downstream IC damage.
Can PESD3V3L4UW,115 protect bidirectional data lines like I²C without additional components?
No - PESD3V3L4UW,115 is unidirectional and only clamps positive transients to ground. For true bidirectional protection of I²C SCL/SDA, a dual-rail configuration (e.g., pairing with a complementary device or using a dedicated bidirectional array like PUSB3FR4) is required to suppress both positive and negative ESD pulses.
Does the 20 kV ESD rating apply to all four channels simultaneously?
Yes - the 20 kV IEC 61000-4-2 contact discharge rating is verified per diode, meaning each cathode-to-anode path withstands 20 kV independently. The device passes full qualification with ten 20 kV pulses applied sequentially to each channel, with no parameter shift beyond datasheet limits.
Is reflow soldering the only acceptable assembly method for SOT665 packages?
Yes - Nexperia specifies reflow soldering only for PESD3V3L4UW,115. Wave soldering is not qualified due to thermal stress risks from the SOT665's flat-lead geometry and thin mold compound; use of wave soldering may cause delamination, solder bridging, or reduced ESD robustness post-assembly.
PESD3V3L4UW,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SOT-665
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V (Max)
- Voltage - Breakdown (Min):
- 5.32V
- Voltage - Clamping (Max) @ Ipp:
- 12V
- Current - Peak Pulse (10/1000µs):
- 3A (8/20µs)
- Power - Peak Pulse:
- 30W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 22pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-665
PESD3V3L4UW,115 FAQ
1.How can I place an order for PESD3V3L4UW,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD3V3L4UW,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD3V3L4UW,115 reliable?
The price and inventory of PESD3V3L4UW,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD3V3L4UW,115 is usually 5 days.
3.What payment methods are accepted for PESD3V3L4UW,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD3V3L4UW,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD3V3L4UW,115?
PESD3V3L4UW,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD3V3L4UW,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD3V3L4UW,115?
For technical support, including PESD3V3L4UW,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD3V3L4UW,115 requirements.
6.How does Aetrix verify that PESD3V3L4UW,115 is sourced from the original manufacturer or authorized distributors?
All PESD3V3L4UW,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD3V3L4UW,115 meets industry standards.
7.What is the process for return or replacement of PESD3V3L4UW,115?
All PESD3V3L4UW,115 units undergo pre-shipment inspection (PSI). If there is an issue with PESD3V3L4UW,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD3V3L4UW,115 part is unused and in its original packaging.
Return procedure for PESD3V3L4UW,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD3V3L4UW,115 Tags

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