Nexperia USA Inc. PESD5V0L2BT,215
- Part No.:
- PESD5V0L2BT,215
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
PESD5V0L2BT,215.pdf
- Description:
- TVS DIODE 5VWM 28VC TO236AB
- Quantity:
- Payment:

- Shipping:

Inventory:51,588
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Product details
Overview
PESD5V0L2BT from Nexperia is a low-capacitance, double bidirectional ESD protection diode in SOT23 package, designed to protect two signal lines against IEC 61000-4-2 (±30 kV contact) and IEC 61000-4-5 (13 A surge) transients, with 75 pF capacitance, 5 V reverse standoff voltage, and 28 V clamping voltage at 13 A - used in high-speed USB, HDMI, and SIM card interfaces.
For engineers reviewing the PESD5V0L2BT datasheet, PESD5V0L2BT pinout, PESD5V0L2BT application, or PESD5V0L2BT equivalent, key selection criteria include bidirectional clamping capability, ultra-low leakage (10 nA), AEC-Q101 qualification, and SOT23 footprint compatibility for space-constrained portable electronics.
Technical Context
This device implements a dual-cathode, common-cathode configuration enabling independent bidirectional protection of two signal lines referenced to ground. Its symmetrical V-I characteristics support ±7.6 V breakdown and ±28 V clamping under 13 A 8/20 µs surge pulses.
Designed for transient suppression on AC-coupled or ground-referenced bidirectional data lines, it operates within −65 °C to +150 °C ambient range and maintains stable performance up to 150 °C junction temperature, with differential resistance of 80 Ω at 1 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 5 V - maximum continuous operating voltage before conduction begins on either polarity |
| Breakdown Voltage | 7.6 V typ - onset of avalanche conduction under 5 mA DC test, ensuring robust margin above 5 V rail |
| Clamping Voltage | 28 V max at 13 A - limits transient voltage across protected line during IEC 61000-4-5 surge event |
| Diode Capacitance | 75 pF at 1 MHz, 0 V - preserves signal integrity on high-speed interfaces like USB 2.0 and audio lines |
| Peak Pulse Power | 350 W - handles short-duration ESD/surge energy without degradation under specified waveform conditions |
| Leakage Current | 10 nA max at 5 V - minimizes DC loading on sensitive analog or RF signal paths |
| ESD Rating | ±30 kV per IEC 61000-4-2 contact discharge - exceeds industrial and automotive immunity requirements |
Pinout & Package
SOT23 plastic surface-mounted package (2.9 mm × 1.3 mm × 1.0 mm body, 1.9 mm pitch); 3-terminal configuration with double cathode architecture optimized for compact PCB layout and minimal trace inductance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | K1 | Cathode for first protected signal line - connects to line 1; anode internally tied to common cathode (pin 3) |
| 2 | K2 | Cathode for second protected signal line - connects to line 2; anode internally tied to common cathode (pin 3) |
| 3 | CC | Common cathode terminal - must be connected to system ground to complete both protection paths |
Key Features
| Feature | Design Value |
|---|---|
| Dual-line bidirectional ESD protection | Single SOT23 device protects two independent signal paths with symmetrical ±30 kV ESD rating |
| Ultra-low signal path capacitance | 75 pF enables use on 480 Mbps USB 2.0, stereo audio, and other >10 MHz signal lines without distortion |
| AEC-Q101 qualification | Validated for automotive subsystems including infotainment and telematics where reliability under thermal cycling is critical |
| Low clamping voltage with high surge current | 28 V clamping at 13 A ensures downstream ICs (e.g., USB transceivers) remain below absolute maximum ratings |
| Sub-10 nA leakage at rated VRWM | Prevents DC bias shift or battery drain in always-on portable and IoT sensor interfaces |
Applications
| USB 2.0 Data Lines | HDMI DDC/CEC Channels |
|---|---|
|
Use Scenario: Protection of differential D+ and D− pins on USB 2.0 host/device connectors exposed to user-handling ESD. IC Role / Device Role: Bidirectional transient voltage suppressor placed directly at connector, shunting ESD current to ground before reaching PHY IC. Use Value: 75 pF capacitance avoids signal rise-time degradation; 28 V clamping prevents damage to 3.3 V tolerant USB transceivers. |
Use Scenario: ESD safeguarding of HDMI DDC (I²C) and CEC control lines in TVs, set-top boxes, and AV receivers. IC Role / Device Role: Dual-line clamp isolating low-voltage control bus from hot-plug and handling transients while preserving I²C timing. Use Value: 10 nA leakage avoids pull-up resistor loading; ±30 kV rating meets IEC 61000-4-2 compliance for consumer electronics. |
| SIM Card Interfaces | Automotive Infotainment Audio |
|
Use Scenario: Protection of SIM VCC, I/O, and CLK lines in mobile handsets and M2M modules subject to repeated card insertion/removal ESD. IC Role / Device Role: Common-cathode dual diode providing simultaneous overvoltage clamping on power and data lines referenced to shared ground. Use Value: SOT23 footprint fits tight SIM socket layouts; AEC-Q101 rating supports automotive telematics module designs. |
Use Scenario: Transient suppression on analog audio input/output lines (e.g., AUX-in, speaker outputs) in car radios and head units. IC Role / Device Role: Low-capacitance bidirectional clamp preventing latch-up or oxide rupture in audio codec inputs during service ESD events. Use Value: 80 Ω differential resistance minimizes insertion loss; 150 °C junction rating supports under-dash thermal environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-line bidirectional ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor ESD9B5.0ST5G | Higher capacitance (120 pF), lower clamping (24 V), same SOT23-3L package and 5 V VRWM | Better for lower-speed lines (e.g., UART, GPIO); less suitable for USB 2.0 due to bandwidth limitation | Select when clamping voltage priority outweighs capacitance constraints and data rate is ≤1 Mbps |
| Vishay ESDD3512-2 | Lower peak pulse current (8 A), higher leakage (100 nA), identical 75 pF and 5 V VRWM | Approved for industrial but not AEC-Q101; limited surge robustness in automotive 12 V system coupling scenarios | Choose for cost-sensitive industrial controls where AEC-Q101 and 13 A surge are not required |
Compared with ESD9B5.0ST5G and ESDD3512-2, PESD5V0L2BT uniquely balances 75 pF capacitance, 13 A surge rating, and AEC-Q101 qualification - making it optimal for automotive-grade USB and HDMI protection where signal fidelity and ruggedness are jointly critical.
Availability
PESD5V0L2BT is available at Aetrix Electronics and suitable for USB 2.0 interface protection, automotive infotainment systems, and portable electronics requiring stable component supply with full traceability and long-term lifecycle support.
Supply support for PESD5V0L2BT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer headquartered in Nijmegen, Netherlands, specializing in high-volume logic, discrete, and MOSFET solutions with emphasis on reliability and efficiency.
PESD5V0L2BT belongs to Nexperia's ESD protection portfolio, engineered specifically for high-speed, space-constrained data line protection in consumer, computing, and automotive electronics.
FAQ
What is the maximum recommended PCB trace length between PESD5V0L2BT and the protected connector?
Trace length should not exceed 3 mm from each protected line (pins 1 and 2) to the connector, and the common cathode (pin 3) must connect directly to a low-inductance ground plane via multiple vias. Longer traces increase inductive voltage overshoot during ESD events, reducing effective clamping performance.
Can PESD5V0L2BT protect unidirectional signals such as UART TX/RX?
Yes - its bidirectional architecture supports unidirectional lines by connecting the signal to pin 1 or 2 and grounding pin 3. It provides symmetrical clamping for positive and negative transients, making it suitable for 3.3 V UART buses where ESD may occur on either polarity relative to ground.
Does PESD5V0L2BT require external series impedance for optimal ESD performance?
No external series resistor is required for basic ESD protection, as the device relies on low dynamic impedance (80 Ω) to clamp transients. However, adding a 0–10 Ω resistor in series can reduce ringing in high-frequency applications - verified in Nexperia's application note AN10742 for USB 2.0 layouts.
Is PESD5V0L2BT compatible with lead-free reflow soldering profiles?
Yes - it is qualified for standard JEDEC J-STD-020D Level 1 reflow, supporting peak temperatures up to 260 °C for ≤30 seconds. The SOT23 package uses matte tin terminations and passes thermal cycling tests from −65 °C to +150 °C per AEC-Q200 requirements.
PESD5V0L2BT,215 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 2
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 7V
- Voltage - Clamping (Max) @ Ipp:
- 28V
- Current - Peak Pulse (10/1000µs):
- 13A (8/20µs)
- Power - Peak Pulse:
- 350W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 75pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TO-236AB
PESD5V0L2BT,215 FAQ
1.How can I place an order for PESD5V0L2BT,215 through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD5V0L2BT,215 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD5V0L2BT,215 reliable?
The price and inventory of PESD5V0L2BT,215 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD5V0L2BT,215 is usually 5 days.
3.What payment methods are accepted for PESD5V0L2BT,215?
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PESD5V0L2BT,215 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD5V0L2BT,215 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD5V0L2BT,215?
For technical support, including PESD5V0L2BT,215 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD5V0L2BT,215 requirements.
6.How does Aetrix verify that PESD5V0L2BT,215 is sourced from the original manufacturer or authorized distributors?
All PESD5V0L2BT,215 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD5V0L2BT,215 meets industry standards.
7.What is the process for return or replacement of PESD5V0L2BT,215?
All PESD5V0L2BT,215 units undergo pre-shipment inspection (PSI). If there is an issue with PESD5V0L2BT,215, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD5V0L2BT,215 part is unused and in its original packaging.
Return procedure for PESD5V0L2BT,215:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD5V0L2BT,215 Tags

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