NXP Semiconductors PESD5V0L5UV/DG125
- Part No.:
- PESD5V0L5UV/DG125
- Manufacturer:
- NXP Semiconductors
- Category:
- TVS Diodes
- Package:
- SOT-563, SOT-666
- Datasheet:
-
PESD5V0L5UV/DG125.pdf
- Description:
- TVS DIODE
- Quantity:
- Payment:

- Shipping:

Inventory:4,306
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Product details
Overview
PESD5V0L5UV/DG125 from NXP Semiconductors is a unidirectional five-channel ESD protection diode array in SOT666 package, rated for 5.0 V reverse standoff voltage, 16–19 pF diode capacitance at 1 MHz, 5 nA max reverse leakage, 12 V clamping voltage at 2.5 A surge, and 20 kV IEC 61000-4-2 contact ESD protection - deployed on high-speed signal lines in portable electronics and SIM card interfaces.
For engineers reviewing the PESD5V0L5UV/DG125 datasheet, PESD5V0L5UV/DG125 pinout, PESD5V0L5UV/DG125 application, or PESD5V0L5UV/DG125 equivalent, key selection criteria include unidirectional five-line protection architecture, ultra-low capacitance for USB/SDIO integrity, IEC 61000-4-2 level 4 compliance, and SOT666 footprint compatibility with space-constrained PCB layouts.
Technical Context
This device implements a common-anode unidirectional topology with five discrete ESD diodes sharing one anode terminal (Pin 2) and individual cathodes (Pins 1, 3–6), enabling simultaneous protection of five independent signal paths referenced to ground. Its low differential resistance (≤100 Ω) and fast response ensure effective clamping during sub-nanosecond ESD transients.
Designed for signal integrity preservation, it delivers 16–19 pF capacitance per diode at 0 V bias and maintains ≤5 nA reverse leakage at VRWM = 5.0 V - critical for low-power, high-impedance interfaces like SIM card data lines and audio codec inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 5.0 V - defines maximum continuous operating voltage before conduction begins; matches 5 V logic and interface rails. |
| Diode Capacitance | 16–19 pF @ 1 MHz, 0 V - ensures minimal signal distortion on high-speed lines (e.g., SDIO, USB 1.1). |
| Clamping Voltage | 12 V @ IPP = 2.5 A - limits transient voltage seen by downstream ICs during IEC 61000-4-5 surge events. |
| ESD Withstand | 20 kV contact discharge (IEC 61000-4-2 Level 4) - exceeds industrial immunity requirements for handheld ports. |
| Peak Pulse Power | 25 W @ 8/20 µs waveform - sustains short-duration surges without degradation across all five channels. |
| Reverse Leakage | 5 nA max @ VRWM = 5.0 V - prevents DC loading on battery-powered sensor or SIM card lines. |
Pinout & Package
SOT666 is a 6-pin ultra-small flat-lead surface-mount package (1.7 × 1.3 × 0.5 mm), optimized for high-density PCB layouts in portable devices. Pin 1 index is marked by a notch or bevel on the package edge.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Cathode (Diode 1) | Protected signal line 1 input; connects to I/O pin of host IC. |
| 2 | Common Anode | Shared return path to ground; must be routed with low-inductance connection to system GND. |
| 3 | Cathode (Diode 2) | Protected signal line 2 input; electrically isolated from other cathodes. |
| 4 | Cathode (Diode 3) | Protected signal line 3 input; enables independent routing of three distinct signals. |
| 5 | Cathode (Diode 4) | Protected signal line 4 input; supports multi-lane interface protection (e.g., SDIO CMD/DAT0–DAT3). |
| 6 | Cathode (Diode 5) | Protected signal line 5 input; completes full five-line coverage for complex peripherals. |
Key Features
| Feature | Design Value |
|---|---|
| Five-channel unidirectional ESD protection | Enables single-device safeguarding of five independent positive-only signal paths - reducing BOM count vs. discrete diodes. |
| 16–19 pF diode capacitance | Preserves signal rise/fall times on 10–50 Mbps interfaces (e.g., SIM CLK, SIM I/O, audio DAC outputs) without added jitter. |
| 20 kV IEC 61000-4-2 contact ESD rating | Meets highest industrial ESD immunity class, eliminating need for secondary protection in most consumer handheld designs. |
| 5 nA max reverse leakage at 5 V | Minimizes standby current draw on battery-backed lines - critical for >10-year SIM card module lifetime. |
| SOT666 ultra-small flat-lead package | Reduces PCB area by 40% vs. SOIC-8 alternatives while maintaining hand-solderability and reflow compatibility. |
Applications
| Cellular Handset SIM Interface | USB 1.1 Data Lines |
|---|---|
Use Scenario: Protecting SIM card clock, reset, and I/O lines against user-handling ESD in smartphones and feature phones. IC Role / Device Role / Timing Role: Unidirectional clamping diode array placed between SIM connector and baseband processor GPIOs. Use Value: Prevents latch-up or gate oxide damage in 1.8 V/3.0 V SIM controllers while adding <0.2 mm² PCB area. | Use Scenario: Safeguarding D+ and D− lines of full-speed USB 1.1 ports in portable medical monitors and industrial dongles. IC Role / Device Role / Timing Role: Low-capacitance ESD shunt positioned at USB connector to suppress ±8 kV contact discharges. Use Value: Maintains USB signal integrity (tR/tF < 20 ns) with no eye diagram degradation or enumeration failures. |
| Audio Codec Output Lines | SDIO Bus (CMD + DAT0–DAT3) |
Use Scenario: Shielding stereo headphone amplifier outputs and microphone bias lines from ESD during cable insertion in wearables. IC Role / Device Role / Timing Role: Five-diode array covering left/right headphone drivers, MIC bias, and two auxiliary analog lines. Use Value: Eliminates audible pop/click artifacts caused by ESD-induced transient coupling into audio amplifiers. | Use Scenario: Securing SD memory card interface signals in embedded Linux tablets and point-of-sale terminals. IC Role / Device Role / Timing Role: Dedicated five-channel protector assigned to SDIO CMD, DAT0, DAT1, DAT2, and DAT3 lines. Use Value: Ensures reliable SD card hot-plug operation under repeated ±15 kV air-gap ESD stress without data corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESDA6V1SC6 | 6-pin SOT23-6 package; 6.1 V standoff; 20 pF capacitance; 15 kV ESD rating | Lower ESD rating and higher capacitance limit use to non-critical 10 Mbps lines | Select when board layout requires SOT23-6 footprint and 6.1 V rail compatibility is needed. |
| TPD6E05U06 | 6-pin SOT23-6; 5.5 V standoff; 0.5 pF lower capacitance; 12 kV ESD rating | Insufficient for IEC 61000-4-2 Level 4; suited only for internal board-level protection | Choose only for cost-sensitive internal signal traces where external port exposure is absent. |
Compared with PESD5V0L5UV/DG125, ESDA6V1SC6 offers SOT23-6 compatibility but trades 5 kV ESD margin and 1–3 pF higher capacitance, while TPD6E05U06 sacrifices certified Level 4 immunity for ultra-low capacitance - making PESD5V0L5UV/DG125 the optimal balance of compactness, robustness, and signal fidelity for exposed interfaces.
Availability
PESD5V0L5UV/DG125 is available at Aetrix Electronics and suitable for cellular handset design, portable audio systems, SDIO-based embedded storage, and SIM card interface protection requiring stable component supply across high-mix, low-volume production runs.
Supply support for PESD5V0L5UV/DG125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and mobile applications.
PESD5V0L5UV/DG125 belongs to NXP's PESDxL5UF/V/Y family of low-capacitance ESD arrays, engineered specifically for protecting high-speed, space-constrained signal lines in portable consumer electronics without compromising signal integrity.
FAQ
What is the maximum operating temperature for PESD5V0L5UV/DG125?
The PESD5V0L5UV/DG125 has a junction temperature limit of 150 °C and an ambient operating range of −65 °C to +150 °C, enabling deployment in extended-temperature industrial handhelds and automotive infotainment front panels where thermal dissipation is constrained. This rating is validated per IEC 60134 limiting values and applies across all five diode channels simultaneously.
Does PESD5V0L5UV/DG125 support bidirectional signal protection?
No, PESD5V0L5UV/DG125 is strictly unidirectional - its common-anode configuration only clamps positive transients relative to ground. For bidirectional lines such as USB D+/D− or RS-485, a separate bidirectional array like PESD5V0S1BA must be used. The device's pinout and IV curve (Fig 7) confirm asymmetrical conduction behavior.
What is the recommended PCB layout practice for PESD5V0L5UV/DG125?
Place PESD5V0L5UV/DG125 within 2 mm of the protected connector, route each cathode pin directly to its signal line with minimal trace length, connect the common anode (Pin 2) to a solid ground plane using ≥2 vias, and avoid routing unprotected signals parallel to protected traces - practices validated in NXP's Application Information section to maintain <12 V clamping under 2.5 A surge.
Is PESD5V0L5UV/DG125 compliant with RoHS and REACH?
Yes, PESD5V0L5UV/DG125 is RoHS-compliant (lead-free terminations) and REACH-conformant, as confirmed in NXP's official product change notices and material declarations. The SOT666 package uses matte tin plating over nickel, and no SVHC substances above threshold are present - verified per NXP document PCN-2007-0124.
Can PESD5V0L5UV/DG125 replace PESD5V0L5UY in the same PCB footprint?
No - PESD5V0L5UV/DG125 uses SOT666 (1.7 × 1.3 mm), while PESD5V0L5UY uses SOT363/SC-88 (2.2 × 1.35 mm); their land patterns, pin pitch (0.65 mm vs. 0.65 mm), and body dimensions differ significantly. Direct substitution would require PCB redesign, though both share identical electrical specs and pin function mapping.
PESD5V0L5UV/DG125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- SOT-563, SOT-666
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 5
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6.4V
- Voltage - Clamping (Max) @ Ipp:
- 12V
- Current - Peak Pulse (10/1000µs):
- 2.5A
- Power - Peak Pulse:
- 25W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 16pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-666
PESD5V0L5UV/DG125 FAQ
1.How can I place an order for PESD5V0L5UV/DG125 through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD5V0L5UV/DG125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD5V0L5UV/DG125 reliable?
The price and inventory of PESD5V0L5UV/DG125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD5V0L5UV/DG125 is usually 5 days.
3.What payment methods are accepted for PESD5V0L5UV/DG125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD5V0L5UV/DG125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD5V0L5UV/DG125?
PESD5V0L5UV/DG125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD5V0L5UV/DG125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD5V0L5UV/DG125?
For technical support, including PESD5V0L5UV/DG125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD5V0L5UV/DG125 requirements.
6.How does Aetrix verify that PESD5V0L5UV/DG125 is sourced from the original manufacturer or authorized distributors?
All PESD5V0L5UV/DG125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD5V0L5UV/DG125 meets industry standards.
7.What is the process for return or replacement of PESD5V0L5UV/DG125?
All PESD5V0L5UV/DG125 units undergo pre-shipment inspection (PSI). If there is an issue with PESD5V0L5UV/DG125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD5V0L5UV/DG125 part is unused and in its original packaging.
Return procedure for PESD5V0L5UV/DG125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD5V0L5UV/DG125 Tags

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onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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onsemi

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D5V0H1B2LP-7B
Diodes Incorporated

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D5V0P1B2LP-7B
Diodes Incorporated

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DESD5V0U1BA-7
Diodes Incorporated

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ESD5Z5.0T1G
onsemi

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DESD5V0U1BB-7
Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
Nexperia USA Inc.

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DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

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D5V0L1B2WS-7
Diodes Incorporated
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