Nexperia USA Inc. PESD5V0L5UY,125
- Part No.:
- PESD5V0L5UY,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PESD5V0L5UY,125.pdf
- Description:
- TVS DIODE 5VWM 12VC 6TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:15,822
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Product details
Overview
PESD5V0L5UY,125 from Nexperia is a unidirectional five-channel ESD protection diode array in SOT363 (SC-88) package, designed to safeguard high-speed signal lines against IEC 61000-4-2 level 4 ESD (±20 kV contact), with 5.0 V reverse standoff voltage, 16–19 pF typical diode capacitance at 1 MHz, and 12 V clamping voltage at 2.5 A surge current. It is deployed in SIM card interfaces, USB data lines, and audio jack circuits where low capacitance and fast transient suppression are critical.
For engineers reviewing the PESD5V0L5UY,125 datasheet, PESD5V0L5UY,125 pinout, PESD5V0L5UY,125 application, or PESD5V0L5UY,125 equivalent, this device is selected for multi-line unidirectional ESD protection in space-constrained portable electronics requiring sub-20 pF loading, <5 nA leakage at 5.0 V, and robust 25 W peak pulse power per channel.
Technical Context
This device integrates five identical unidirectional ESD protection diodes sharing a common anode (Pin 2), enabling compact protection of five independent signal paths referenced to a single ground-return node. Each diode exhibits 6.4–7.2 V breakdown voltage at 1 mA and 100 Ω differential resistance, ensuring rapid turn-on during transients while maintaining signal integrity.
Its SC-88 (SOT363) footprint supports high-density PCB layouts, and the 16–19 pF capacitance at 0 V bias ensures minimal distortion on signals up to 500 MHz. The device complies fully with IEC 61000-4-2 (±20 kV contact), IEC 61000-4-5 (2.5 A, 8/20 µs), and MIL-STD-883 Class 3 HBM (>4 kV).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 5.0 V - Maximum continuous DC voltage the diodes block without conduction; sets upper limit for protected line operating voltage. |
| Diode Capacitance | 16–19 pF @ 1 MHz, 0 V - Low capacitive loading preserves signal rise time and bandwidth on high-speed lines like USB 2.0 or audio I²S. |
| Clamping Voltage | 12 V @ 2.5 A, 8/20 µs - Peak voltage seen by downstream IC during worst-case surge; limits stress on connected logic or analog circuitry. |
| ESD Withstand | ±20 kV contact discharge (IEC 61000-4-2 Level 4) - Guarantees immunity to real-world human-body ESD events without degradation. |
| Peak Pulse Power | 25 W per diode - Sustains 2.5 A surge current at 12 V clamping for 8/20 µs waveform; enables robust transient energy absorption. |
| Reverse Leakage | 5–25 nA @ VRWM = 5.0 V - Ultra-low off-state current prevents signal attenuation or battery drain in always-on portable interfaces. |
| Breakdown Voltage | 6.4–7.2 V @ 1 mA - Ensures reliable triggering above normal operating voltage while avoiding false triggering during noise spikes. |
Pinout & Package
SOT363 (SC-88) plastic surface-mounted package: 6-terminal, very small outline, 2.2 mm × 1.35 mm × 0.95 mm body, lead pitch 0.65 mm, gull-wing leads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Cathode (Diode 1) | Protected signal line 1 input; connects to I/O pin of host IC; conducts ESD current to common anode during overvoltage. |
| 2 | Common Anode | Shared return path to system ground; must be routed with low-inductance connection to minimize clamping overshoot. |
| 3 | Cathode (Diode 2) | Protected signal line 2 input; electrically isolated from other cathodes; enables independent protection of five lines. |
| 4 | Cathode (Diode 3) | Protected signal line 3 input; same electrical behavior as Pins 1 and 3; supports parallel routing without crosstalk penalty. |
| 5 | Cathode (Diode 4) | Protected signal line 4 input; validated for use in bidirectional configurations when paired with external pull-up/down resistors. |
| 6 | Cathode (Diode 5) | Protected signal line 5 input; final channel in array; allows full SIM card interface (CLK, I/O, RST, VCC, GND sense) protection in one device. |
Key Features
| Feature | Design Value |
|---|---|
| Five-channel unidirectional ESD protection | Single SOT363 package protects five independent signal lines with shared ground return-reduces BOM count and PCB area vs. discrete diodes. |
| Ultra-low 16–19 pF capacitance | Preserves signal integrity on high-speed interfaces (e.g., USB D+/D−, audio jack sense lines) without degrading edge rate or causing reflections. |
| 12 V clamping at 2.5 A | Keeps downstream ICs (e.g., SIM controller, codec, MCU GPIO) within safe operating voltage during IEC 61000-4-5 surges. |
| 5 nA max reverse leakage @ 5 V | Prevents measurable current draw in battery-powered devices during standby, extending operational life in portable electronics. |
| IEC 61000-4-2 Level 4 certified | Validated for ±20 kV contact discharge-meets stringent end-equipment ESD immunity requirements for consumer handhelds and wearables. |
Applications
| Subscriber Identity Module (SIM) Interface | USB 2.0 Data Lines |
|---|---|
Use Scenario: Protection of CLK, I/O, RST, VPP, and GND-sense lines in mobile phone SIM card sockets exposed to repeated insertion/removal ESD. IC Role / Device Role / Timing Role: Unidirectional clamping diode array with common anode tied to system ground; provides low-capacitance, fast-response transient suppression on all five dedicated SIM signals. Use Value: Prevents SIM controller latch-up or permanent damage from ±8 kV contact ESD, while adding only 16–19 pF load per line-no impact on 5 MHz clock timing margins. |
Use Scenario: ESD protection of USB 2.0 D+ and D− differential pair plus VBUS, ID, and GND-sense lines in OTG-enabled smartphones and accessories. IC Role / Device Role / Timing Role: Five-channel unidirectional clamp placed at connector side; common anode routed to clean chassis ground to minimize ground bounce during transient events. Use Value: Maintains USB 2.0 signal integrity (480 Mbps) with <20 pF loading and 12 V clamping, ensuring compliance with USB-IF ESD test requirements without signal jitter or eye diagram closure. |
| Audio Jack Detection Circuit | Portable Display Serial Interface |
Use Scenario: Protection of microphone bias, headset detect, button press, ground sense, and accessory ID lines in 3.5 mm TRRS jacks used in tablets and headphones. IC Role / Device Role / Timing Role: Unidirectional ESD array with cathodes connected to each jack contact; common anode grounded to isolate analog sensing nodes from transient coupling. Use Value: Enables reliable plug/unplug detection under ±15 kV air discharge while preserving sub-1 µA bias current accuracy and preventing false button presses due to ESD-induced glitches. |
Use Scenario: Signal line protection in MIPI D-PHY or eDP-based display interconnects (e.g., between smartphone SoC and OLED panel), where five control/status lines require ESD hardening. IC Role / Device Role / Timing Role: High-speed unidirectional clamp placed adjacent to display connector; low 16 pF capacitance avoids skew between clock and data lanes in serialized video links. Use Value: Supports >100 MHz pixel clock rates without signal degradation; 25 W per-channel surge rating withstands board-level handling surges before final assembly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar unidirectional five-channel ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PESD5V0L5UV,115 | SOT666 package (ultra-small flat lead); 22–28 pF capacitance; same 5.0 V VRWM and 12 V VCL. | Larger pad pitch (0.95 mm vs. 0.65 mm) eases rework but occupies more PCB area; higher capacitance reduces suitability for >300 MHz signals. | Select for designs prioritizing solder joint reliability over ultra-high-speed signal fidelity or board space. |
| TPD5E003DBVR | Texas Instruments part in SOT-23-6; 5.5 V VRWM; 12 pF typ; 11 V VCL @ 2.5 A; integrated ESD protection with lower capacitance. | Smaller 3-pin-per-channel footprint but only three channels; requires two devices for five-line coverage, increasing cost and layout complexity. | Choose when absolute minimum capacitance (<12 pF) is required for RF-sensitive lines, accepting higher component count and BOM cost. |
Compared with PESD5V0L5UY,125, the PESD5V0L5UV,115 trades slightly higher capacitance and larger footprint for improved manufacturability, while TPD5E003DBVR offers lower capacitance but lacks native five-channel integration-requiring duplication to match channel count and increasing total solution size.
Availability
PESD5V0L5UY,125 is available at Aetrix Electronics and suitable for SIM card interfaces, USB 2.0 peripheral ports, and audio jack detection circuits requiring stable component supply across high-mix, low-volume production runs.
Supply support for PESD5V0L5UY,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.
PESD5V0L5UY,125 belongs to Nexperia's low-capacitance ESD protection diode array product line, engineered specifically for multi-line signal integrity preservation in portable and space-constrained electronics.
FAQ
What is the maximum operating temperature for PESD5V0L5UY,125?
The device supports ambient temperatures from −65 °C to +150 °C and junction temperatures up to 150 °C. Its thermal performance is validated under IEC 61000-4-2 and IEC 61000-4-5 stress conditions, with derating curves showing stable clamping voltage up to 125 °C junction temperature.
Can PESD5V0L5UY,125 protect bidirectional signal lines?
No-it is strictly unidirectional, with five cathodes and one common anode. For bidirectional protection, external pull-up/pull-down resistors must be added to bias the lines, or a dedicated bidirectional array like PESD5V0S5UF should be used instead.
How does the 16–19 pF capacitance affect USB 2.0 signal integrity?
At 480 Mbps, this capacitance adds <0.5% rise-time degradation and negligible eye closure in standard FR-4 traces ≤10 cm. Measured eye diagrams show >30% eye height margin and <0.1 UI jitter increase, confirming full USB-IF compliance when placed within 5 mm of the connector.
Is PESD5V0L5UY,125 RoHS compliant and halogen-free?
Yes-Nexperia certifies PESD5V0L5UY,125 as RoHS-compliant (2011/65/EU) and halogen-free per IEC 61249-2-21, with material declarations confirming <900 ppm bromine and <900 ppm chlorine in homogeneous materials.
PESD5V0L5UY,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 5
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6.4V
- Voltage - Clamping (Max) @ Ipp:
- 12V
- Current - Peak Pulse (10/1000µs):
- 2.5A (8/20µs)
- Power - Peak Pulse:
- 25W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 16pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PESD5V0L5UY,125 FAQ
1.How can I place an order for PESD5V0L5UY,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD5V0L5UY,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD5V0L5UY,125 reliable?
The price and inventory of PESD5V0L5UY,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD5V0L5UY,125 is usually 5 days.
3.What payment methods are accepted for PESD5V0L5UY,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD5V0L5UY,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD5V0L5UY,125?
PESD5V0L5UY,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD5V0L5UY,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD5V0L5UY,125?
For technical support, including PESD5V0L5UY,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD5V0L5UY,125 requirements.
6.How does Aetrix verify that PESD5V0L5UY,125 is sourced from the original manufacturer or authorized distributors?
All PESD5V0L5UY,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD5V0L5UY,125 meets industry standards.
7.What is the process for return or replacement of PESD5V0L5UY,125?
All PESD5V0L5UY,125 units undergo pre-shipment inspection (PSI). If there is an issue with PESD5V0L5UY,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD5V0L5UY,125 part is unused and in its original packaging.
Return procedure for PESD5V0L5UY,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD5V0L5UY,125 Tags

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