Nexperia USA Inc. PESD5V0S2UQ,115
- Part No.:
- PESD5V0S2UQ,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SOT-663
- Datasheet:
-
PESD5V0S2UQ,115.pdf
- Description:
- TVS DIODE 5VWM 20VC SOT663
- Quantity:
- Payment:

- Shipping:

Inventory:14,961
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Product details
Overview
PESD5V0S2UQ,115 from Nexperia is a unidirectional double ESD protection diode in SOT663 package, designed to protect two signal lines against IEC 61000-4-2 level 4 ESD (±30 kV contact), with 5 V reverse standoff voltage, 150 W peak pulse power (8/20 μs), and 150–215 pF capacitance - deployed in high-speed data lines and audio/video interfaces.
For engineers reviewing the PESD5V0S2UQ,115 datasheet, PESD5V0S2UQ,115 pinout, PESD5V0S2UQ,115 application, or PESD5V0S2UQ,115 equivalent, key selection criteria include clamping voltage at 15 A (20 V), low leakage (<300 nA at 5 V), dual-cathode/common-anode topology, and SOT663 footprint compatibility for space-constrained PCB layouts.
Technical Context
This device implements a dual-unidirectional ESD clamp architecture with a shared anode (Pin 3) and separate cathodes (Pins 1 and 2), enabling independent protection of two signal paths referenced to common ground. Its low differential resistance (≤15 Ω) ensures rapid voltage clamping during transients.
It complies with IEC 61000-4-2 (±30 kV contact), IEC 61000-4-5 (15 A surge, 8/20 μs), and MIL-STD-883 HBM (>10 kV), while maintaining signal integrity via capacitance under 215 pF at 1 MHz and VR = 0 V - critical for USB 2.0, HDMI, and parallel port applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VRWM | 5 V - maximum continuous reverse operating voltage before leakage rises significantly; sets upper limit for protected line DC bias. |
| VCL @ IPP = 15 A | 20 V - clamped voltage during 8/20 μs surge; defines worst-case overvoltage seen by downstream ICs. |
| Cd @ 1 MHz, VR = 0 V | 150–215 pF - total diode capacitance per channel; impacts signal rise time and insertion loss on high-speed lines. |
| IPP max | 15 A - peak surge current per diode supported without failure; validated per IEC 61000-4-5. |
| PPP max | 150 W - peak pulse power dissipation capability per diode at tp = 8/20 μs; determines transient energy handling margin. |
| IRM @ VRWM | <300 nA - reverse leakage at rated standoff voltage; minimizes DC loading on sensitive analog or low-power logic inputs. |
| ESD rating | ±30 kV contact discharge (IEC 61000-4-2 Level 4); qualifies for industrial and consumer equipment requiring highest ESD immunity. |
Pinout & Package
Package: SOT663 - ultra-small flat-lead surface-mount package (1.7 × 1.3 × 0.5 mm), optimized for high-density PCB layouts and automated assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Cathode 1 | Protected signal line 1 output node; connects to I/O pin requiring unidirectional clamping to ground. |
| 2 | Cathode 2 | Protected signal line 2 output node; enables independent protection of second data path (e.g., D+ and D−). |
| 3 | Common anode | Shared ground reference terminal; must be connected directly to low-impedance system ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel unidirectional ESD protection | Single SOT663 device protects two independent signal lines with dedicated cathodes and shared anode - reduces component count vs. discrete diodes. |
| Low clamping voltage (20 V @ 15 A) | Ensures downstream ICs (e.g., USB transceivers, audio codecs) remain within absolute maximum ratings during ESD events. |
| Ultra-low leakage (<300 nA @ 5 V) | Prevents signal degradation or false triggering in high-impedance or battery-powered circuits. |
| Controlled capacitance (150–215 pF) | Preserves signal integrity on data lines up to 480 Mbps (USB 2.0 full-speed) without excessive jitter or attenuation. |
| IEC 61000-4-2 Level 4 compliance | Validated for ±30 kV contact discharge - meets stringent immunity requirements for CE-marked industrial and consumer end equipment. |
Applications
| USB 2.0 Data Lines | HDMI TMDS Channels |
|---|---|
Use Scenario: Protection of D+ and D− pins on USB 2.0 host/device connectors exposed to user-handling ESD. IC Role / Device Role / Timing Role: Unidirectional transient voltage suppressor placed at connector entry point, clamping surges before reaching PHY IC. Use Value: Prevents latch-up or gate oxide damage in USB transceivers while maintaining <100 ps propagation delay and minimal signal distortion. |
Use Scenario: ESD safeguarding of three TMDS differential pairs and clock line in HDMI source/sink ports. IC Role / Device Role / Timing Role: Dual-diode array per TMDS pair (e.g., one PESD5V0S2UQ per pair), grounded via common anode to minimize return path inductance. Use Value: Enables HDMI 1.4 compliance with ≤0.1 dB insertion loss at 225 MHz and no measurable eye diagram degradation. |
| Parallel Printer Port | Audio Line Inputs |
Use Scenario: Protection of 8-bit bidirectional data bus (D0–D7), control signals (STROBE, ACK), and status lines (BUSY, ERROR) on legacy parallel ports. IC Role / Device Role / Timing Role: One device per signal group (e.g., D0/D1 on one PESD5V0S2UQ), with cathodes tied to each line and common anode to chassis ground. Use Value: Eliminates field failures due to operator-induced ESD on printer cables while supporting 1.5 MB/s transfer rates without timing skew. |
Use Scenario: Input-stage protection for line-level analog audio (L/R channels) on consumer AV receivers and DACs. IC Role / Device Role / Timing Role: Clamping diode pair between each input and ground, leveraging low leakage to avoid DC offset or noise injection into op-amp front-end. Use Value: Maintains THD+N < 0.002% at 1 kHz and preserves 20 Hz–20 kHz frequency response without capacitive loading artifacts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel unidirectional ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD5V3U2U-2/TR | Higher VRWM (5.3 V), lower Cd (110 pF typ), same SOT663 package and 30 kV ESD rating. | Better suited for 5 V tolerant I/O with tighter capacitance budget (e.g., MIPI D-PHY). | Select when signal bandwidth exceeds 800 MHz and clamping voltage margin allows 5.3 V standoff. |
| TPD2E001DRYR | Lower VCL (12 V @ 1 A), higher Cd (190 pF typ), same dual-cathode topology but TI-specific packaging. | Optimized for lower-voltage clamping in 3.3 V systems; less effective at 15 A surge due to lower PPP (80 W). | Choose only if system-level testing confirms 12 V clamping suffices and 3.3 V rail operation dominates. |
Compared with ESD5V3U2U-2/TR and TPD2E001DRYR, PESD5V0S2UQ,115 offers balanced trade-offs: moderate capacitance for USB/audio use cases, robust 15 A surge handling, and industry-standard Nexperia reliability - making it ideal for cost-sensitive, high-volume industrial and consumer designs where 5 V signal rails and IEC 61000-4-2 Level 4 are mandatory.
Availability
PESD5V0S2UQ,115 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI TMDS safeguarding, and parallel port ESD hardening requiring stable component supply across production lifecycles.
Supply support for PESD5V0S2UQ,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-performance, reliable standard products including ESD protection, logic, discretes, and MOSFETs - serving automotive, industrial, and consumer markets with scalable manufacturing.
The PESDxS2UQ series targets compact, high-efficiency ESD protection for multi-line interfaces, emphasizing low capacitance, repeatable clamping, and SOT663 footprint compatibility for next-generation portable and connectivity devices.
FAQ
What is the maximum recommended PCB trace length between PESD5V0S2UQ,115 and the protected connector?
Trace length should not exceed 3 mm from device cathode to connector pin and 2 mm from common anode to solid ground plane. Longer traces increase inductance, degrading clamping response and allowing voltage overshoot above VCL during fast ESD events - verified per IEC 61000-4-2 test setup guidelines in the datasheet.
Can PESD5V0S2UQ,115 protect bidirectional signal lines like RS-232 or CAN?
No - it is unidirectional only, with cathodes tied to signal lines and common anode to ground. Bidirectional protection requires either two devices back-to-back or a dedicated bidirectional array (e.g., PESD5V0X2U). Using this part on bidirectional lines risks forward conduction and signal corruption during negative transients.
Does PESD5V0S2UQ,115 require external series impedance for optimal ESD performance?
No external resistor is required for basic ESD clamping, but a 0 Ω or low-value (≤10 Ω) resistor may be added in series with each cathode to dampen ringing in high-frequency applications. The device's low differential resistance (15 Ω) and integrated design eliminate need for external RC networks in most USB/audio implementations.
How does junction temperature affect leakage current in PESD5V0S2UQ,115?
Reverse leakage increases exponentially with temperature: IRM remains <300 nA at 25 °C but rises to ~15 nA at 150 °C (per datasheet Fig 7). This is well within safe limits for most applications, though designers should verify thermal design in sealed enclosures where ambient exceeds 85 °C.
PESD5V0S2UQ,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SOT-663
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6.4V
- Voltage - Clamping (Max) @ Ipp:
- 20V
- Current - Peak Pulse (10/1000µs):
- 15A (8/20µs)
- Power - Peak Pulse:
- 150W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 150pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-663
PESD5V0S2UQ,115 FAQ
1.How can I place an order for PESD5V0S2UQ,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD5V0S2UQ,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD5V0S2UQ,115 reliable?
The price and inventory of PESD5V0S2UQ,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD5V0S2UQ,115 is usually 5 days.
3.What payment methods are accepted for PESD5V0S2UQ,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD5V0S2UQ,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD5V0S2UQ,115?
PESD5V0S2UQ,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD5V0S2UQ,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD5V0S2UQ,115?
For technical support, including PESD5V0S2UQ,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD5V0S2UQ,115 requirements.
6.How does Aetrix verify that PESD5V0S2UQ,115 is sourced from the original manufacturer or authorized distributors?
All PESD5V0S2UQ,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD5V0S2UQ,115 meets industry standards.
7.What is the process for return or replacement of PESD5V0S2UQ,115?
All PESD5V0S2UQ,115 units undergo pre-shipment inspection (PSI). If there is an issue with PESD5V0S2UQ,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD5V0S2UQ,115 part is unused and in its original packaging.
Return procedure for PESD5V0S2UQ,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD5V0S2UQ,115 Tags

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DESD3V3E1BL-7B
Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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Nexperia USA Inc.

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Toshiba Semiconductor and Storage

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Diodes Incorporated
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