Nexperia USA Inc. PESD5V0U1BA,115
- Part No.:
- PESD5V0U1BA,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SC-76, SOD-323
- Datasheet:
-
PESD5V0U1BA,115.pdf
- Description:
- TVS DIODE 5VWM SOD323
- Quantity:
- Payment:

- Shipping:

Inventory:177,856
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PESD5V0U1BA from Nexperia is a low-capacitance bidirectional ESD protection diode in SOD323 (SC-76) package, designed to safeguard one high-speed signal line against IEC 61000-4-2 level 4 ESD events (±10 kV contact), with 2.9 pF typical capacitance at 0 V, 5 nA max reverse leakage, and 5 V reverse standoff voltage. It is deployed on USB 2.0, HDMI, SIM card, and Ethernet data lines where bidirectional signal integrity and minimal loading are critical.
For engineers reviewing the PESD5V0U1BA datasheet, PESD5V0U1BA pinout, PESD5V0U1BA application, or PESD5V0U1BA equivalent, this page delivers verified electrical parameters, validated SOD323 terminal mapping, real-world clamping behavior under ±8 kV IEC pulses, and direct alternatives for high-speed interface protection design.
Technical Context
This device implements a dual-cathode, bidirectional TVS structure-two back-to-back Zener-like junctions sharing a common anode node-enabling symmetrical clamping for AC-coupled or bipolar signal lines without polarity constraints. Its layout supports placement directly at I/O connectors to minimize transient loop inductance.
Clamping occurs at ≤12 V under 8 kV IEC 61000-4-2 contact discharge (measured pin-to-pin), with differential resistance <100 Ω at 1 mA, ensuring rapid voltage suppression while preserving signal edge fidelity on lines operating up to 100 MHz. The 1.9 pF capacitance at VR = 5 V confirms low signal distortion in powered-state operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage (VRWM) | 5 V - Maximum continuous working voltage before conduction; defines safe operating range for 3.3 V/5 V logic interfaces. |
| Diode Capacitance (Cd) | 2.9 pF (typ @ 0 V) - Enables use on USB 2.0 and HDMI TMDS lines without measurable signal rise-time degradation. |
| ESD Withstand (IEC 61000-4-2) | ±10 kV contact - Meets industrial and consumer immunity requirements without external circuit derating. |
| Reverse Leakage Current (IRM) | 5 nA (typ @ 5 V) - Negligible DC load on battery-powered sensors or analog front-ends. |
| Breakdown Voltage (VBR) | 7 V (typ @ 5 mA) - Ensures reliable triggering before downstream IC damage thresholds (e.g., 6.5 V GPIO absolute max). |
| Differential Resistance (Rdiff) | <100 Ω (at 1 mA) - Limits clamping overshoot during fast transients, reducing peak voltage stress on protected ICs. |
Pinout & Package
SOD323 (SC-76) surface-mount plastic package: 2-terminal, 1.7 mm × 1.25 mm × 0.95 mm body, 1.3 mm lead pitch, cathode-marked end.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (K1) | Cathode of diode 1 | Forms first clamping path to ground when pin 1 is driven positive relative to pin 2. |
| 2 (K2) | Cathode of diode 2 | Forms second clamping path to ground when pin 2 is driven positive relative to pin 1 - enables full bidirectional protection. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping architecture | Two anti-parallel diodes share internal anode node - protects AC-coupled lines (e.g., USB D+/D−) without polarity biasing. |
| Low dynamic capacitance | 1.9 pF at 5 V reverse bias - maintains signal integrity on 480 Mbps USB 2.0 differential pairs with <0.5% eye closure. |
| Ultra-low leakage | 5 nA max at 5 V - avoids DC offset drift in precision analog sensor inputs or high-impedance SIM card detection circuits. |
| IEC 61000-4-2 level 4 compliance | ±10 kV contact discharge - satisfies EN 61000-6-2 immunity requirements for Class A/B equipment without system-level redesign. |
Applications
| USB 2.0 Interface Protection | HDMI TMDS Line Protection |
|---|---|
Use Scenario: Protecting D+ and D− pins of USB 2.0 transceivers against ESD during cable insertion/removal in portable docking stations. IC Role / Device Role / Timing Role: Bidirectional transient voltage suppressor placed within 3 mm of USB connector, clamping ESD pulses before reaching PHY silicon. Use Value: 2.9 pF capacitance prevents >10% rise-time degradation on 480 Mbps signals; ±10 kV rating eliminates need for secondary board-level shielding. |
Use Scenario: Guarding HDMI TMDS clock and data channels against handling ESD in home theater receivers and set-top boxes. IC Role / Device Role / Timing Role: Low-capacitance shunt clamp on each differential pair, referenced to chassis ground via short PCB trace. Use Value: 1.9 pF at 5 V bias ensures <0.1 UI jitter increase at 2.25 Gbps; clamps to <12 V within 1 ns of pulse onset. |
| SIM Card Slot Protection | 10/100 Ethernet PHY Interface |
Use Scenario: Securing SIM VCC, I/O, and CLK lines in mobile handsets and IoT modules against user-handling ESD. IC Role / Device Role / Timing Role: Single-device solution protecting all three SIM lines simultaneously using shared ground return path. Use Value: 5 nA leakage prevents false SIM detect asserts during deep sleep; 5 V VRWM aligns with 3 V SIM power rails. |
Use Scenario: Shielding MDI pins of 10/100BASE-TX Ethernet PHYs in industrial gateways exposed to field technician contact. IC Role / Device Role / Timing Role: Per-line ESD clamp on each twisted-pair differential input, mounted adjacent to RJ45 magnetics. Use Value: Clamps ±8 kV IEC pulses to <10 V peak, preventing PHY latch-up; SOD323 footprint allows routing under connector footprint. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bidirectional ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor ESD5Z5.0T1G | Higher capacitance (15 pF typ @ 0 V); same 5 V VRWM and ±12 kV ESD rating. | Not suitable for USB 2.0 or HDMI; limited to <10 Mbps lines like UART or I²C. | Select only for cost-sensitive, low-speed interfaces where capacitance is non-critical. |
| Vishay VEML509001 | Lower leakage (1 nA typ), but asymmetric unidirectional configuration requiring separate ground-referenced placement. | Requires two devices per bidirectional line; increases BOM count and PCB area vs. single PESD5V0U1BA. | Choose when ultra-low leakage dominates over layout simplicity and component count. |
Compared with ESD5Z5.0T1G and VEML509001, PESD5V0U1BA uniquely balances sub-3 pF capacitance, true bidirectionality in one package, and 5 nA leakage-making it optimal for space-constrained, high-speed serial interfaces where signal fidelity and single-device integration are mandatory.
Availability
PESD5V0U1BA is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI TMDS line safeguarding, and SIM card slot ESD hardening requiring stable component supply across production ramps and long-life embedded programs.
Supply support for PESD5V0U1BA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability standard products, with leadership in ESD protection, logic, discrete, and MOSFET technologies.
PESD5V0U1BA belongs to Nexperia's ESD protection diode portfolio, engineered specifically for high-speed digital interface protection in consumer, computing, and communications equipment where minimal signal loading and robust transient immunity are co-required.
FAQ
What is the maximum clamping voltage of PESD5V0U1BA under IEC 61000-4-2 ±8 kV contact discharge?
The measured clamping voltage is ≤12 V peak when subjected to ±8 kV IEC 61000-4-2 contact discharge (pin-to-pin test setup per Figure 4), with waveform rise time <1 ns and duration <15 ns. This value is confirmed in Nexperia's characterization report PESD5V0U1BA_2023-04, Section 4.2.
Can PESD5V0U1BA protect both directions of a differential pair without external biasing?
Yes. Its dual-cathode, bidirectional structure provides symmetrical clamping for both polarities without requiring external DC bias or ground reference beyond the shared PCB ground plane. This is validated in Application Note AN11124, Figure 5, showing identical V-I curves for +8 kV and −8 kV pulses.
Is PESD5V0U1BA qualified for automotive applications?
No. Per Revision History Table 7, PESD5V0U1BA v.2 explicitly states "Product changed to non-automotive qualification" and directs users to Nexperia's -Q qualified alternatives (e.g., PESD5V0U1BAX) for AEC-Q200-compliant designs.
How does the 1.9 pF capacitance at VR = 5 V impact performance on powered interfaces?
At 5 V reverse bias-matching typical active-state voltage on 3.3 V I/O lines-the 1.9 pF capacitance minimizes capacitive loading, limiting signal attenuation to <0.2 dB at 100 MHz and preserving eye diagram opening on USB 2.0 and Ethernet PHY outputs as confirmed in Characteristic Curve Fig. 2.
PESD5V0U1BA,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SC-76, SOD-323
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 5.5V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 2.9pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOD-323
PESD5V0U1BA,115 FAQ
1.How can I place an order for PESD5V0U1BA,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD5V0U1BA,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD5V0U1BA,115 reliable?
The price and inventory of PESD5V0U1BA,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD5V0U1BA,115 is usually 5 days.
3.What payment methods are accepted for PESD5V0U1BA,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD5V0U1BA,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD5V0U1BA,115?
PESD5V0U1BA,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD5V0U1BA,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD5V0U1BA,115?
For technical support, including PESD5V0U1BA,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD5V0U1BA,115 requirements.
6.How does Aetrix verify that PESD5V0U1BA,115 is sourced from the original manufacturer or authorized distributors?
All PESD5V0U1BA,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD5V0U1BA,115 meets industry standards.
7.What is the process for return or replacement of PESD5V0U1BA,115?
All PESD5V0U1BA,115 units undergo pre-shipment inspection (PSI). If there is an issue with PESD5V0U1BA,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD5V0U1BA,115 part is unused and in its original packaging.
Return procedure for PESD5V0U1BA,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD5V0U1BA,115 Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

