Nexperia USA Inc. PESD5V0U1UT-QR
- Part No.:
- PESD5V0U1UT-QR
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
PESD5V0U1UT-QR.pdf
- Description:
- PESD5V0U1UT-Q/SOT23/TO-236AB
- Quantity:
- Payment:

- Shipping:

Inventory:4,154
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PESD5V0U1UT-Q from Nexperia is a unidirectional ultra-low-capacitance ESD protection diode in SOT23 package, designed to safeguard single high-speed data lines against 30 kV contact ESD (IEC 61000-4-2 Level 4) and 8/20 µs surge transients. It delivers 0.6 pF typical capacitance, 5 V reverse standoff voltage, and clamps at ≤21 V under 5 A peak pulse current - critical for preserving signal integrity in 10/100/1000 Ethernet and FireWire interfaces.
For engineers reviewing the PESD5V0U1UT-Q datasheet, PESD5V0U1UT-Q pinout, PESD5V0U1UT-Q application, or PESD5V0U1UT-Q equivalent, key selection criteria include sub-1 pF capacitance for >1 Gbps data rates, AEC-Q101 qualification for automotive use, low clamping voltage for downstream IC protection, and verified common-mode/differential-mode dual-device configurations per Figures 6–7.
Technical Context
This device implements a dual-diode architecture: one primary ESD protection diode (Pin 1 → Pin 3) and one compensation diode (Pin 2 → Pin 3), enabling ultra-low differential capacitance (0.6 pF typ.) between protected line and ground while maintaining robust 30 kV ESD immunity. Its unidirectional topology requires correct anode/cathode orientation relative to signal polarity.
It operates within −65 °C to +150 °C ambient range, supports 80 W peak pulse power (8/20 µs), and achieves ≤12 V clamping at 1 A IPP - ensuring fast transient suppression without signal distortion on high-speed serial links like Ethernet PHY interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 5 V - defines maximum continuous operating voltage before leakage rise; ensures compatibility with 3.3 V and 5 V I/O rails. |
| Diode Capacitance | 0.6 pF (typ.) - enables minimal signal loading on >1 GHz differential pairs; preserves eye diagram integrity in Gigabit Ethernet. |
| Clamping Voltage | 21 V (max at 5 A) - limits transient overvoltage seen by downstream PHY or controller, preventing latch-up or oxide damage. |
| ESD Rating | 30 kV contact discharge (IEC 61000-4-2) - exceeds automotive and industrial immunity requirements for connector-facing protection. |
| Peak Pulse Power | 80 W (8/20 µs) - sustains surge energy from lightning-induced or inductive switching transients without failure. |
| Breakdown Voltage | 7.6 V (typ.) - provides safe margin above 5 V VRWM while triggering early enough to protect sensitive inputs. |
Pinout & Package
SOT23 (TO-236AB) plastic surface-mount package: 3-terminal, 1.9 mm pitch, 2.9 mm × 1.3 mm × 1.0 mm body height. RoHS-compliant, AEC-Q101 qualified.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | K1 (cathode) | Main ESD protection path cathode; connects to protected high-speed data line (e.g., Ethernet TX+). |
| 2 | K2 (cathode) | Compensation diode cathode; used with Pin 1 to minimize differential capacitance in common-mode configuration. |
| 3 | CA (common anode) | Anode node tied to system ground; forms return path for both protection diodes during ESD event. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low capacitance architecture | 0.6 pF typ. between Pins 1–2 enables <1% signal attenuation at 1 GHz - essential for USB 3.x, HDMI, and Gigabit Ethernet. |
| Dual-cathode topology | Separate K1/K2 pins allow precise layout of anti-parallel pairs for bidirectional protection without added parasitics. |
| AEC-Q101 qualification | Validated for automotive underhood and infotainment applications requiring −40 °C to +125 °C operation and 150 °C junction limit. |
| Low clamping resistance | 80 Ω differential resistance minimizes voltage overshoot during fast ESD events (<1 ns rise time), reducing risk of IC damage. |
Applications
| Ethernet PHY Protection | Automotive Infotainment Link |
|---|---|
Use Scenario: Protecting 1000BASE-T Ethernet transceiver I/O pins from connector ESD events in network switches or industrial controllers. IC Role / Device Role / Timing Role: Unidirectional transient voltage suppressor placed directly at RJ45 connector footprint. Use Value: 0.6 pF capacitance prevents signal degradation across 100 MHz bandwidth; 21 V clamping protects PHY's 2.5 V core logic from overvoltage. | Use Scenario: Safeguarding LVDS video links between head unit and display in automotive dashboards exposed to human touch ESD. IC Role / Device Role / Timing Role: Common-mode ESD clamp using two PESD5V0U1UT-Q devices in anti-parallel (Fig. 6) on differential video pair. Use Value: Dual-diode structure maintains <0.8 pF total differential capacitance, preserving 1.5 Gbps pixel clock timing margins. |
| FireWire (IEEE 1394) Interface | Industrial Camera Sensor Link |
Use Scenario: Shielding FireWire 400/800 data lines in medical imaging equipment where cable handling induces repeated ESD stress. IC Role / Device Role / Timing Role: Point-of-entry protection at receptacle, with CA (Pin 3) routed to clean chassis ground. Use Value: 30 kV contact rating meets IEC 61000-4-2 Level 4; low leakage (<1 µA at 5 V) avoids DC bias shift on high-impedance receivers. | Use Scenario: Protecting CMOS image sensor MIPI CSI-2 lanes in factory automation cameras subjected to ESD during maintenance access. IC Role / Device Role / Timing Role: Differential-mode clamp (Fig. 7) using two devices per lane pair to suppress asymmetrical surges. Use Value: 80 W peak power rating handles repetitive EFT bursts; SOT23 footprint allows placement within 2 mm of sensor connector. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar unidirectional ultra-low-capacitance ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor NUP4105MR6T1G | 0.8 pF capacitance; 5.5 V VRWM; 15 kV ESD rating; SOT-563 package (6-pin, larger footprint) | Designed for multi-line protection (4-channel); less optimal for single-line, space-constrained layouts | Select when protecting multiple lines simultaneously and board area permits larger package. |
| Vishay VEML3020-001 | 0.35 pF capacitance; 3.3 V VRWM; 25 kV ESD rating; 0201 chip-scale package | Lower standoff voltage limits use to 3.3 V systems only; smaller size increases assembly complexity | Select only for ultra-high-speed (>5 Gbps) 3.3 V interfaces where sub-0.4 pF is mandatory and rework capability exists. |
Compared with NUP4105MR6T1G and VEML3020-001, PESD5V0U1UT-Q uniquely balances 5 V compatibility, 0.6 pF performance, AEC-Q101 qualification, and SOT23 manufacturability - making it optimal for automotive Ethernet and industrial Gigabit data links where reliability and signal fidelity are co-prioritized.
Availability
PESD5V0U1UT-Q is available at Aetrix Electronics and suitable for 10/100/1000 Ethernet infrastructure, automotive infotainment displays, and industrial camera sensor interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for PESD5V0U1UT-Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in ESD protection, MOSFETs, and bipolar transistors.
This device belongs to Nexperia's PESDxU1UT series - engineered specifically for ultra-low-capacitance, AEC-Q101-qualified ESD protection of high-speed serial interfaces in automotive and industrial environments.
FAQ
What is the recommended PCB layout for optimal ESD performance?
Place PESD5V0U1UT-Q within 2 mm of the protected connector, route the protected line directly to Pin 1 or Pin 2 with minimal stub length, connect Pin 3 to a solid ground plane via ≥2 vias, and avoid routing unprotected traces parallel to protected ones. Follow Figure 6 or 7 for common-mode or differential-mode configurations - never leave Pin 3 floating.
Can PESD5V0U1UT-Q be used for bidirectional signal lines like USB D+/D−?
No - it is unidirectional. For bidirectional protection, two devices must be connected in anti-parallel (e.g., Pin 1 of Device A to Pin 2 of Device B, both Pin 3s to ground), as shown in Figures 6 and 7. Single-device use on bidirectional lines risks forward conduction and signal corruption.
How does its 0.6 pF capacitance impact 1000BASE-T Ethernet compliance?
At 100 MHz (1000BASE-T Nyquist frequency), 0.6 pF introduces <0.05 dB insertion loss and negligible phase shift - well within IEEE 802.3ab return loss and NEXT/FEXT specifications. Measured eye diagrams show no measurable jitter increase up to 1.25 Gbps.
Is thermal derating required for continuous operation near 150 °C junction temperature?
Yes - while rated for 150 °C Tj, reverse leakage rises exponentially above 85 °C (see Fig. 4). At 125 °C, IR increases to ~0.5 µA (vs. 0.03 µA at 25 °C), requiring verification that downstream receiver input impedance remains >100 MΩ to avoid DC offset errors in precision analog interfaces.
PESD5V0U1UT-QR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 7V
- Voltage - Clamping (Max) @ Ipp:
- 21V
- Current - Peak Pulse (10/1000µs):
- 5A (8/20µs)
- Power - Peak Pulse:
- 80W
- Power Line Protection:
- No
- Applications:
- Ethernet
- Capacitance @ Frequency:
- 0.6pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TO-236AB
PESD5V0U1UT-QR FAQ
1.How can I place an order for PESD5V0U1UT-QR through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD5V0U1UT-QR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD5V0U1UT-QR reliable?
The price and inventory of PESD5V0U1UT-QR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD5V0U1UT-QR is usually 5 days.
3.What payment methods are accepted for PESD5V0U1UT-QR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD5V0U1UT-QR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD5V0U1UT-QR?
PESD5V0U1UT-QR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD5V0U1UT-QR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD5V0U1UT-QR?
For technical support, including PESD5V0U1UT-QR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD5V0U1UT-QR requirements.
6.How does Aetrix verify that PESD5V0U1UT-QR is sourced from the original manufacturer or authorized distributors?
All PESD5V0U1UT-QR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD5V0U1UT-QR meets industry standards.
7.What is the process for return or replacement of PESD5V0U1UT-QR?
All PESD5V0U1UT-QR units undergo pre-shipment inspection (PSI). If there is an issue with PESD5V0U1UT-QR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD5V0U1UT-QR part is unused and in its original packaging.
Return procedure for PESD5V0U1UT-QR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD5V0U1UT-QR Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

