Nexperia USA Inc. PESD5V0X1BT,215
- Part No.:
- PESD5V0X1BT,215
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
PESD5V0X1BT,215.pdf
- Description:
- TVS DIODE 5VWM TO236AB
- Quantity:
- Payment:

- Shipping:

Inventory:10,326
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Product details
Overview
PESD5V0X1BT from Nexperia is an ultra-low-capacitance bidirectional ESD protection diode in SOT23 package, designed to protect one high-speed signal line (e.g., USB 2.0 or RF antenna trace) against IEC 61000-4-2 level 4 ESD events up to ±9 kV, with 0.9 pF typical capacitance at 0 V, 5 V reverse standoff voltage, and 1 nA leakage current at 5 V.
For engineers reviewing the PESD5V0X1BT datasheet, PESD5V0X1BT pinout, PESD5V0X1BT application, or PESD5V0X1BT equivalent, this device is selected for high-frequency signal integrity preservation in USB, Ethernet, SIM card, and RF front-end protection where sub-1 pF capacitance and low clamping voltage are critical.
Technical Context
This dual-cathode, common-anode ESD diode supports two distinct configurations: bidirectional protection across pins 1–2 (for AC-coupled or bipolar signal lines), and unidirectional protection across pins 1–3 or 2–3 (for two independent positive-only signal paths). Its symmetrical V-I characteristics enable robust clamping under both polarities of transient stress.
The device operates within −55 °C to +150 °C ambient range, features 100 Ω differential resistance at 1 mA, and maintains stable capacitance (<1.3 pF) up to 5 V reverse bias-enabling minimal signal distortion on 10/100/1000 Mbit/s Ethernet and high-speed data interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 5 V - Maximum continuous operating voltage before conduction; ensures no interference with 3.3 V or 5 V logic signaling. |
| Diode Capacitance (bidir) | 0.9 pF (typ.) at 1 MHz, 0 V - Preserves signal integrity on >500 MHz RF traces and USB 2.0 differential pairs. |
| ESD Withstand (IEC 61000-4-2) | ±9 kV contact discharge - Meets industrial and consumer end-equipment immunity requirements without external circuitry. |
| Reverse Leakage Current | 1 nA (typ.) at 5 V - Prevents DC loading on sensitive analog or RF bias networks. |
| Breakdown Voltage | 7.5 V (typ.) at 5 mA - Defines onset of clamping; enables safe margin above 5 V VRWM for transient suppression. |
| Differential Resistance | 100 Ω (max.) at 1 mA - Limits voltage overshoot during fast transients, supporting low-clamp performance. |
Pinout & Package
SOT23 plastic surface-mounted package (2.9 mm × 1.3 mm × 1.0 mm body, 1.9 mm lead pitch); thermally optimized for reflow soldering per IPC-J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | K1 (cathode of diode 1) | Connects to first protected signal line in bidirectional mode or first unidirectional line; forms low-impedance path to common anode during ESD event. |
| 2 | K2 (cathode of diode 2) | Connects to second protected signal line in unidirectional mode or same line as K1 in bidirectional configuration; enables dual-line or single-line protection flexibility. |
| 3 | CA (common anode) | Ground reference terminal; must be connected directly to low-inductance system ground plane to ensure effective transient shunting and minimal clamping voltage rise. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional single-line protection | Enables ESD hardening of AC-coupled or differential signals (e.g., USB D+/D−) without polarity constraints. |
| Unidirectional dual-line capability | Allows protection of two independent positive-rail signal paths (e.g., SIM CLK & SIM I/O) using one device and shared ground return. |
| 0.9 pF typical capacitance | Minimizes insertion loss and phase distortion on 480 Mbps USB 2.0 and 1 Gbps Ethernet channels. |
| 1 nA max reverse leakage | Prevents signal degradation in high-impedance RF detector or antenna tuning circuits. |
| IEC 61000-4-2 level 4 compliance | Validated for ±9 kV contact discharge-meets EN 61000-6-2 and FCC Part 15 Class B immunity requirements. |
Applications
| USB 2.0 Interface Protection | RF Antenna Front-End Protection |
|---|---|
Use Scenario: Protecting D+ and D− lines of a portable USB host controller against user-handling ESD events. IC Role / Device Role / Timing Role: Bidirectional transient voltage suppressor placed immediately adjacent to USB connector, clamping ESD pulses before reaching PHY IC. Use Value: 0.9 pF capacitance avoids signal rise-time degradation, maintaining eye diagram compliance at 480 Mbps while surviving ±8 kV IEC contact discharge. |
Use Scenario: Shielding LTE/5G antenna feedline from electrostatic discharge in smartphone bezel-integrated designs. IC Role / Device Role / Timing Role: Low-capacitance ESD clamp between antenna port and RF switch/LNA input, referenced to chassis ground. Use Value: Sub-1 pF capacitance preserves VSWR and insertion loss below 3.8 GHz; 1 nA leakage prevents DC bias shift in active antenna tuners. |
| 10/100/1000BASE-T Ethernet PHY | SIM Card Interface Protection |
Use Scenario: Safeguarding MDI differential pairs in enterprise PoE switch PHYs exposed to field service ESD. IC Role / Device Role / Timing Role: Dual-cathode clamp configured in bidirectional mode across each pair, minimizing inter-pair skew. Use Value: Symmetric clamping (<±9 kV) and matched capacitance (<1.3 pF) maintain TDR impedance continuity and reduce bit error rate under transient stress. |
Use Scenario: Securing SIM VCC, I/O, and CLK lines in mobile payment terminals subject to frequent card insertion/removal. IC Role / Device Role / Timing Role: Unidirectional protector using pins 1–3 and 2–3 to cover three critical SIM signals with single SOT23 footprint. Use Value: Enables compact layout with <0.5 mm trace length to ground; 5 V VRWM aligns with ISO/IEC 7816-3 supply tolerance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection diode applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor NUP4105MR6T1G | Higher capacitance (3.5 pF typ.), higher leakage (50 nA), but rated for ±15 kV ESD. | Better suited for lower-speed interfaces (e.g., UART, I²C) where clamping robustness outweighs capacitance sensitivity. | Select when ESD threat exceeds ±9 kV and signal bandwidth <100 MHz. |
| Vishay VEML6030X01 | Not applicable - optical sensor, not ESD diode; excluded from valid alternatives. | N/A | Not a functional alternative; omitted due to incorrect device category. |
Compared with NUP4105MR6T1G, PESD5V0X1BT delivers superior high-frequency performance (0.9 pF vs. 3.5 pF) and lower leakage (1 nA vs. 50 nA), making it optimal for USB 2.0, RF, and Gigabit Ethernet; NUP4105MR6T1G trades capacitance for higher ESD rating in cost-sensitive, lower-bandwidth applications.
Availability
PESD5V0X1BT is available at Aetrix Electronics and suitable for USB 2.0 interface protection, RF antenna front-end safeguarding, and SIM card interface hardening requiring stable component supply, consistent SOT23 packaging, and guaranteed ESD immunity compliance.
Supply support for PESD5V0X1BT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in ESD protection, MOSFETs, and bipolar transistors.
PESD5V0X1BT belongs to Nexperia's ultra-low-capacitance ESD protection portfolio, engineered specifically for preserving signal fidelity in high-speed digital and RF interfaces while meeting stringent IEC 61000-4-2 immunity requirements.
FAQ
What is the maximum operating temperature for PESD5V0X1BT?
The PESD5V0X1BT supports operation from −55 °C to +150 °C ambient temperature, with junction temperature limited to 150 °C. This range accommodates deployment in automotive under-hood modules, industrial gateways, and handheld devices with internal thermal dissipation constraints.
Can PESD5V0X1BT protect two independent signal lines simultaneously?
Yes-when used in unidirectional configuration, pins 1–3 and 2–3 each form independent ESD protection paths to the common anode (pin 3), enabling simultaneous safeguarding of two positive-rail signals such as SIM CLK and SIM I/O, provided both share the same ground reference.
How does PESD5V0X1BT's capacitance vary with applied voltage?
Capacitance remains stable at 0.9 pF (typ.) from 0 V to 5 V reverse bias in bidirectional mode; in unidirectional mode, it rises to 1.7–2.3 pF over the same range. This behavior is documented in Figures 2 and 3 of the official Nexperia datasheet v.3 (April 2023).
Is PESD5V0X1BT qualified for automotive applications?
No-per Revision History section 13, PESD5V0X1BT was changed to non-automotive qualification in v.3 (April 2023). For automotive use, Nexperia offers the PESD5V0X1BQ variant, which undergoes AEC-Q101 stress testing and is explicitly designated for automotive-grade systems.
PESD5V0X1BT,215 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 5.8V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- -
- Capacitance @ Frequency:
- 0.9pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TO-236AB
PESD5V0X1BT,215 FAQ
1.How can I place an order for PESD5V0X1BT,215 through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD5V0X1BT,215 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD5V0X1BT,215 reliable?
The price and inventory of PESD5V0X1BT,215 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD5V0X1BT,215 is usually 5 days.
3.What payment methods are accepted for PESD5V0X1BT,215?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD5V0X1BT,215 transactions.
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4.How is shipping managed for PESD5V0X1BT,215?
PESD5V0X1BT,215 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD5V0X1BT,215 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD5V0X1BT,215?
For technical support, including PESD5V0X1BT,215 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD5V0X1BT,215 requirements.
6.How does Aetrix verify that PESD5V0X1BT,215 is sourced from the original manufacturer or authorized distributors?
All PESD5V0X1BT,215 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD5V0X1BT,215 meets industry standards.
7.What is the process for return or replacement of PESD5V0X1BT,215?
All PESD5V0X1BT,215 units undergo pre-shipment inspection (PSI). If there is an issue with PESD5V0X1BT,215, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD5V0X1BT,215 part is unused and in its original packaging.
Return procedure for PESD5V0X1BT,215:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD5V0X1BT,215 Tags

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