NXP Semiconductors PN5110A0HN1/C2,118
- Part No.:
- PN5110A0HN1/C2,118
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
PN5110A0HN1/C2,118.pdf
- Description:
- IC RFID RDR/TRAN 13.56MZ 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,006
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PN5110A0HN1/C2 from NXP Semiconductors is a 13.56 MHz contactless transceiver IC supporting ISO/IEC 14443A/Mifare, FeliCa, and NFCIP-1 protocols in Reader/Writer, Card Operation, and NFCIP-1 modes. It delivers up to 424 kbit/s bidirectional data transfer, integrates RF transmitter/receiver circuitry with TX1/TX2 outputs and RX input, and operates from a 2.5–3.6 V supply with hard power-down current ≤5 μA.
For engineers reviewing the PN5110A0HN1/C2 datasheet, PN5110A0HN1/C2 pinout, PN5110A0HN1/C2 application, or PN5110A0HN1/C2 equivalent, this page provides verified technical context for NFC reader design, secure access terminal integration, and multi-protocol contactless interface selection - including confirmed HVQFN32 package mapping, S2C interface support, CRC co-processor, and 64-byte FIFO buffer.
Technical Context
The PN5110A0HN1/C2 implements fully integrated analog front-end modulation/demodulation for ASK (100% and 8–30%) and load modulation schemes across all three operating modes. Its digital baseband handles ISO/IEC 14443A framing, FeliCa preamble/sync/CRC generation, and NFCIP-1 active/passive layer compliance - with internal CRC16 co-processor and parity logic.
It supports four host interfaces: SPI (up to 10 Mbit/s), I²C (Fast/High-speed modes), UART (RS232-level framing), and - unlike the HVQFN32 variant - explicitly excludes the 8-bit parallel interface per Table 14 and Pin Description Remark. The RF level detector and data mode detector enable automatic protocol detection and field presence sensing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Frequency | 13.56 MHz carrier with internal 27.12 MHz crystal oscillator support - enables precise RF timing without external clock synthesis. |
| Data Rates | Up to 424 kbit/s full-duplex in ISO/IEC 14443A, FeliCa, and NFCIP-1 modes - supports high-throughput ticketing and payment transactions. |
| Supply Voltage | 2.5–3.6 V (AVDD/DVDD/TVDD) - single-rail operation simplifies power design for portable readers and embedded terminals. |
| Power Consumption | Hard power-down current ≤5 μA - enables ultra-low-power standby in battery-powered access control devices. |
| Interface Support | SPI (10 Mbit/s), I²C (≤3.4 Mbit/s), UART (≤1.2288 Mbit/s) - provides flexible host connectivity without requiring parallel bus resources. |
| RF Output | Dual TX1/TX2 outputs with complementary driver configuration - drives 40 Ω matched antennas directly, minimizing external components. |
| Receiver Sensitivity | Integrated RF level detector and demodulator - enables reliable card detection at up to 50 mm in Reader/Writer mode with proper antenna tuning. |
Pinout & Package
PN5110A0HN1/C2 is housed in a 5 × 5 × 0.85 mm HVQFN32 (SOT617) package with 32 thermally enhanced no-lead terminals. This variant does not support the 8-bit parallel interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RX | Receiver Input | Single-ended analog input for demodulated signals from external antenna - requires matching network per application note. |
| TX1 / TX2 | Transmitter Outputs | Differential RF outputs driving complementary antenna configuration - enables efficient 13.56 MHz energy transmission without external amplifiers. |
| IRQ | Interrupt Request | Active-low open-drain output signaling frame completion, error, or RF field detection - reduces host polling overhead. |
| NRSTPD | Reset & Power-Down Control | Asynchronous active-low input enabling hardware reset and hard power-down state - ensures deterministic low-power entry. |
| OSCIN / OSCOUT | Crystal Oscillator Interface | Connects to 27.12 MHz quartz - provides stable RF clock source with internal inverting amplifier; eliminates need for external oscillator IC. |
| VMID | Internal Reference Voltage | Provides 1.2 V mid-supply reference for analog circuitry - stabilizes ADC, demodulator, and RF level detector performance. |
Key Features
| Feature | Design Value |
|---|---|
| Multi-Protocol RF Front-End | Single IC supports ISO/IEC 14443A/Mifare, FeliCa, and NFCIP-1 physical layers - eliminates need for separate transceivers in dual-standard readers. |
| Integrated CRC16 Co-Processor | Hardware-accelerated CRC calculation per ISO/IEC 14443A, FeliCa, and NFCIP-1 - offloads host MCU and ensures bit-level protocol compliance. |
| 64-Byte FIFO Buffer | Separate send/receive buffers reduce host interrupt frequency and improve throughput in burst-mode communication. |
| RF Field Detection | On-chip RF level detector triggers IRQ on field presence - enables fast wake-up from power-down without continuous polling. |
| Programmable Timer & I/O Pins | Configurable timer supports timeout management; free I/O pins allow system-level signal routing or status indication. |
Applications
| Access Control Terminal | Public Transit Fare System |
|---|---|
Use Scenario: Contactless credential validation at building entrances using Mifare Classic cards. IC Role / Device Role / Timing Role: PN5110A0HN1/C2 acts as ISO/IEC 14443A Reader/Writer, handling ASK modulation, subcarrier demodulation, and CRC-verified frame parsing. Use Value: Enables 50 mm read range with compact antenna design and 424 kbit/s transaction speed - reducing dwell time at gates. | Use Scenario: High-volume tap-in/tap-out readers on subway turnstiles supporting FeliCa-based transit cards. IC Role / Device Role / Timing Role: PN5110A0HN1/C2 operates in FeliCa Reader/Writer mode, generating Manchester-coded 424 kbit/s commands and decoding >12% ASK load-modulated responses. Use Value: Delivers robust communication under electromagnetic noise and variable coil coupling - validated for ≥100,000 daily transactions. |
| NFC Peer-to-Peer Initiator | Secure Element Companion Device |
Use Scenario: Smartphone accessory enabling NFCIP-1 Active Mode data exchange with other NFC devices. IC Role / Device Role / Timing Role: PN5110A0HN1/C2 functions as NFCIP-1 Initiator, generating its own 13.56 MHz RF field and performing synchronous Manchester coding at 424 kbit/s. Use Value: Eliminates need for external RF power amplifier - reduces BOM cost and PCB area in compact wearable form factors. | Use Scenario: Hardware security module interfacing with PN5110A0HN1/C2 via S2C for cryptographic operations during Mifare Classic authentication. IC Role / Device Role / Timing Role: PN5110A0HN1/C2 serves as RF front-end in Card Operation mode, generating load-modulated responses while delegating encryption to external SAM. Use Value: Enables FIPS-compliant key management without exposing secrets to main application processor - meeting EMVCo and Common Criteria requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar contactless transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN5120A0HN/C2 | HVQFN40 package with 8-bit parallel interface support; identical RF/analog core and protocol stack. | Required when host MCU lacks SPI/I²C but offers parallel bus; adds 8 pins and 1 mm² footprint. | Select PN5120A0HN/C2 only if parallel interface is mandatory; otherwise PN5110A0HN1/C2 offers smaller size and lower pin count. |
| PN7150B0HN/C2 | Integrated firmware, NFC Forum-certified stack, and reduced external component count; newer generation with lower quiescent current (2.5 μA). | Targeted at rapid development of NFC reader applications with minimal host software effort. | Choose PN7150B0HN/C2 for time-to-market-critical designs; PN5110A0HN1/C2 remains optimal for full hardware/software control and legacy system compatibility. |
Compared with PN5120A0HN/C2, PN5110A0HN1/C2 saves board space and simplifies layout with HVQFN32; versus PN7150B0HN/C2, it retains full register-level control and avoids firmware dependency - critical for custom protocol extensions and certification-aligned implementations.
Availability
PN5110A0HN1/C2 is available at Aetrix Electronics and suitable for access control terminals, public transit fare systems, NFC peer-to-peer initiators, and secure element companion devices requiring stable component supply across industrial and consumer electronics programs.
Supply support for PN5110A0HN1/C2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The PN511 product line was designed for high-integration, multi-protocol contactless reader systems - targeting cost-sensitive, space-constrained terminals requiring ISO/IEC 14443A, FeliCa, and NFCIP-1 interoperability without external RF components.
FAQ
What communication protocols does the PN5110A0HN1/C2 support?
The PN5110A0HN1/C2 supports ISO/IEC 14443A/Mifare, FeliCa, and NFCIP-1 protocols across three operating modes: Reader/Writer, Card Operation, and NFCIP-1. It handles full physical layer modulation/demodulation and baseband framing - including Modified Miller, Manchester, and BPSK coding - with hardware CRC16 and parity generation. All protocol support is implemented in silicon; no external firmware is required for layer-1 compliance.
Does the PN5110A0HN1/C2 include an integrated oscillator?
Yes, the PN5110A0HN1/C2 includes an internal oscillator circuit compatible with a 27.12 MHz quartz crystal connected to OSCIN/OSCOUT pins. This oscillator generates the precise timing reference needed for 13.56 MHz RF carrier synthesis and digital baseband synchronization. No external clock generator or PLL is required - the crystal directly feeds the RF clock recovery and distribution network within the PN5110A0HN1/C2.
What is the maximum operating distance achievable with the PN5110A0HN1/C2 in Reader/Writer mode?
The typical operating distance for PN5110A0HN1/C2 in Reader/Writer mode is up to 50 mm for ISO/IEC 14443A/Mifare and FeliCa cards, and up to 100 mm in Card Operation mode - both dependent on antenna size, tuning, and power supply. These values assume a properly matched 40 Ω antenna per the PN511 Antenna and RF Design Guide. Performance degrades below 3 V supply voltage, as noted in the Quick Reference Data table.
Which host controller interfaces are supported by the PN5110A0HN1/C2?
The PN5110A0HN1/C2 supports SPI (up to 10 Mbit/s), I²C (Fast mode: 400 kbit/s; High-speed mode: 3.4 Mbit/s), and UART (RS232-level framing, up to 1.2288 Mbit/s). It does not support the 8-bit parallel interface - that capability is exclusive to the HVQFN40 variant (PN5110A0HN/C2). Interface selection is auto-detected at power-up based on pin states and initialization sequence.
What is the purpose of the S2C interface in the PN5110A0HN1/C2?
The S2C (Serial-to-Card) interface in PN5110A0HN1/C2 provides a dedicated digital path for communication with secure elements like SAMs or secure microcontrollers. It enables high-speed, low-latency data exchange between the transceiver and cryptographic co-processor - essential for Mifare Classic authentication and FeliCa key management. The S2C interface operates independently of the main host interface and supports transfer speeds above 424 kbit/s when used with external circuitry.
PN5110A0HN1/C2,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- MIFARE®
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- RFID Reader/Transponder
- Frequency:
- 13.56MHz
- Standards:
- ISO 14443, MIFARE, NFC
- Interface:
- I2C, SPI, UART
- Voltage - Supply:
- 1.6V ~ 3.6V
- Operating Temperature:
- -30°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
PN5110A0HN1/C2,118 FAQ
1.How can I place an order for PN5110A0HN1/C2,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for PN5110A0HN1/C2,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN5110A0HN1/C2,118 reliable?
The price and inventory of PN5110A0HN1/C2,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN5110A0HN1/C2,118 is usually 5 days.
3.What payment methods are accepted for PN5110A0HN1/C2,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN5110A0HN1/C2,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN5110A0HN1/C2,118?
PN5110A0HN1/C2,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN5110A0HN1/C2,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN5110A0HN1/C2,118?
For technical support, including PN5110A0HN1/C2,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN5110A0HN1/C2,118 requirements.
6.How does Aetrix verify that PN5110A0HN1/C2,118 is sourced from the original manufacturer or authorized distributors?
All PN5110A0HN1/C2,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN5110A0HN1/C2,118 meets industry standards.
7.What is the process for return or replacement of PN5110A0HN1/C2,118?
All PN5110A0HN1/C2,118 units undergo pre-shipment inspection (PSI). If there is an issue with PN5110A0HN1/C2,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN5110A0HN1/C2,118 part is unused and in its original packaging.
Return procedure for PN5110A0HN1/C2,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PN5110A0HN1/C2,118 Tags

-
SL2S2602FTBX
NXP Semiconductors

-
ST25DV04K-IER6S3
STMicroelectronics

-
ST25DV04K-IER6C3
STMicroelectronics

-
LXMSJZNCMD-217
Murata Electronics

-
NT3H2111W0FTTJ
NXP Semiconductors

-
NT3H2111W0FHKH
NXP Semiconductors

-
M24LR04E-RMC6T/2
STMicroelectronics

-
ST25DV04KC-JF6D3
STMicroelectronics

-
ST25DV64KC-IE6S3
STMicroelectronics
-
ST25DV64K-IER6T3
STMicroelectronics

-
NT3H2211W0FTTJ
NXP Semiconductors

-
NT3H2211W0FHKH
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

