NXP Semiconductors PN5190B1EV/C121Y
- Part No.:
- PN5190B1EV/C121Y
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 64-VFBGA
- Datasheet:
-
PN5190B1EV/C121Y.pdf
- Description:
- NFC FRONTEND SUPPORTING CHALLENG
- Quantity:
- Payment:

- Shipping:

Inventory:3,186
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PN5190B1EV/C121Y from NXP Semiconductors is a high-power NFC frontend IC supporting ISO/IEC 14443-A/B, FeliCa, ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, NFC-IP1/2, and MIFARE card family R/W - with hardware-accelerated crypto, dynamic power control (DPC), and adaptive waveshape control (AWC). It operates at 13.56 MHz with up to 2.3 W RF output power and targets secure payment terminals and access control readers.
For engineers reviewing the PN5190B1EV/C121Y datasheet, PN5190B1EV/C121Y pinout, PN5190B1EV/C121Y application, or PN5190B1EV/C121Y equivalent, key selection considerations include its VFBGA64 package (4.5 mm × 4.5 mm × 0.80 mm), SPI host interface (15 Mbit/s), ultra-low-power card detection (22 μA avg), integrated DC-DC for VDDPA up to 6.0 V, and firmware version 2.1 pre-installed with encrypted download support.
Technical Context
The PN5190B1EV/C121Y implements a fully integrated 13.56 MHz RF frontend with independent TX/RX buffers (1024 bytes each), hardware-based cryptographic acceleration for MIFARE Classic/Plus/DESFire/Ultralight, and autonomous real-time features including DPC and AWC - eliminating host dependency during field regulation and waveform shaping. Its PLL supports external clock inputs (24/32/48 MHz) in lieu of a 27.12 MHz crystal.
It integrates a step-up DC-DC converter (2.8–6.0 V output) synchronized to the receiver clock to suppress switching noise, enabling stable high-power operation even under battery droop. The chip supports both low-power card detection (LPCD) and ultra-low-power card detection (ULPCD), though ULPCD disables DC-DC usage and restricts GPIO3 to abort-only function.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Protocols | Fully compliant with ISO/IEC 14443-A/B, FeliCa (212/424 kbit/s), ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, NFC-IP1/2, and all MIFARE families - enabling universal contactless reader design. |
| Transmit Power | Up to 2.3 W RF output power without DC-DC; enables >10 cm read range for ISO14443-A cards in optimized antenna layouts. |
| Host Interface | SPI at up to 15 Mbit/s with dedicated IRQ line and separate 1024-byte TX/RX buffers - reduces host CPU load and latency for high-throughput NFC transactions. |
| Power Consumption | 22 μA average current in ULPCD mode (330 ms polling); enables multi-year battery life in portable access readers and smart locks. |
| Supply Voltage | VDDIO: 2.4–3.6 V (3.3 V nominal); VBAT: 2.4–5.5 V (1.8 V option supported); VDDPA: up to 6.0 V via integrated DC-DC - simplifies single-supply system architecture. |
| Firmware | Pre-programmed with FW v2.1 (default for volume production); supports encrypted firmware download and EEPROM-configurable DPC, LPCD, and P2P timing parameters. |
| Operating Temp | −40 °C to +105 °C ambient (TX current = 120 mA @ VDDPA = 3.6 V); qualified for industrial and automotive-grade embedded reader modules. |
Pinout & Package
VFBGA64 package: plastic very thin fine-pitch ball grid array, 64 balls, 4.5 mm × 4.5 mm × 0.80 mm body, MSL=3, delivered on 13″ reel. Thermal pad (central heatsink) must be connected to GND for thermal and EMI performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| H5, H4 | RXP, RXN | Differential receiver inputs - require matched 50 Ω trace routing and 100 nF AC-coupling caps to ground for optimal SNR. |
| H1, H3 | TX1, TX2 | Differential antenna driver outputs - connect directly to matching network; support up to 2.3 W output into 50 Ω load. |
| G1, F1, A1 | VDDPA, VUP_TX, BOOST_LX | Transmitter supply chain: VDDPA powers PA core; VUP_TX feeds TX_LDO; BOOST_LX connects to boost inductor for DC-DC operation. |
| E6–D5 | ATX_A–ATX_D | SPI target interface (MISO/MOSI/SCK/NSS) - supports 15 Mbit/s full-duplex with hardware flow control via IRQ. |
| B7 | IRQ | Open-drain interrupt output - signals packet completion, error, or card detection event to host without polling overhead. |
| F8, G8 | XTAL1, XTAL2 | 27.12 MHz crystal interface - or configure PLL for 24/32/48 MHz external clock input to eliminate crystal BOM cost. |
| H6 | VMID | Antenna symmetry point connection - must be AC-coupled via 100 nF cap to antenna ground for balanced field generation. |
| D7 | GPIO3 | ULPCD abort control only when ULPCD active; otherwise available as general-purpose I/O with configurable pull-up/down. |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic Power Control (DPC) | Real-time regulation of VDDPA based on antenna loading - maintains constant field strength while minimizing chip power dissipation and thermal stress. |
| Adaptive Waveshape Control (AWC) | Hardware-adjusted modulation envelope per protocol - improves interoperability with diverse tags/cards without host intervention or firmware update. |
| Ultra-Low-Power Card Detection (ULPCD) | 22 μA average current at 330 ms polling interval - enables battery-powered devices to achieve >5-year operational life before replacement. |
| Integrated DC-DC Converter | Step-up regulator (2.8–6.0 V) synchronized to receiver clock - eliminates external DC-DC noise coupling and enables single 3.3 V supply for full 2.3 W RF output. |
| MIFARE Crypto Hardware Engine | Dedicated accelerator for MIFARE Classic 1K/4K, Plus, DESFire EV1/EV2, and Ultralight - offloads host CPU and ensures EMVCo L1 compliance for payment terminals. |
Applications
| Payment Terminals | Physical Access Readers |
|---|---|
Use Scenario: Contactless EMV payment terminal in retail kiosk or unattended vending machine. IC Role / Device Role / Timing Role: NFC frontend handling ISO14443-A/B and FeliCa protocols, performing secure MIFARE DESFire EV2 authentication and transaction framing. Use Value: 2.3 W RF output enables reliable 8–10 cm read range across card orientations; DPC maintains field stability during metal interference; FW v2.1 meets EMVCo L1 analog test requirements. | Use Scenario: Battery-powered door lock or gate controller requiring multi-year operation on two AA cells. IC Role / Device Role / Timing Role: Autonomous card detector and reader executing ULPCD, LPCD, and full ISO14443-A R/W without host wake-up. Use Value: 22 μA ULPCD current extends battery life beyond 5 years; integrated DC-DC sustains 3.6 V VDDPA during battery voltage sag; GPIO3 provides hardware abort for fast wake-from-standby. |
| e-Government ID Readers | Transportation Fare Validators |
Use Scenario: Portable ePassport or national ID verification device used by border agents or field officers. IC Role / Device Role / Timing Role: High-reliability NFC frontend supporting ISO14443-B (ePassport) and ISO15693 (contactless ID cards), with hardware crypto for PKI signature verification. Use Value: Dual-protocol support ensures compatibility with global eID standards; −40 °C to +105 °C rating enables outdoor use in extreme climates; SPI interface allows integration with low-power ARM Cortex-M host. | Use Scenario: Handheld transit validator used by conductors to check stored-value cards (FeliCa, MIFARE) on buses or trains. IC Role / Device Role / Timing Role: Multi-protocol reader executing FeliCa 424 kbit/s and MIFARE Classic 1K R/W with real-time AWC compensation for varying card distances. Use Value: 424 kbit/s FeliCa speed enables sub-300 ms validation; AWC adapts waveform dynamically to card position - reducing retry failures during rapid tap-and-go motion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC frontend applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7160B1HN/C121Y | Lower RF output (1.2 W), no integrated DC-DC, VFLGA40 package (5 mm × 5 mm), FW v2.1 preloaded. | Targeted at cost-sensitive, space-constrained readers where <8 cm range suffices and external DC-DC is acceptable. | Select when board area and BOM cost outweigh need for maximum range and single-supply simplicity. |
| ST25R3916B | 1.5 W max RF output, no MIFARE crypto hardware, supports ISO14443-A/B/F, FeliCa, and ISO15693; QFN32 package. | Designed for industrial readers requiring robust analog front-end but not certified MIFARE support or EMVCo compliance. | Select when open-standard NFC (not MIFARE-dependent) and lower certification burden are priorities over proprietary card support. |
Compared with PN7160B1HN/C121Y and ST25R3916B, the PN5190B1EV/C121Y delivers higher RF power, integrated DC-DC for single-supply operation, and hardware-accelerated MIFARE crypto - making it the only choice for EMVCo-certified payment terminals and long-range access systems requiring ULPCD.
Availability
PN5190B1EV/C121Y is available at Aetrix Electronics and suitable for payment terminals, physical access readers, and e-government ID validators requiring stable component supply, long-term lifecycle support, and EMVCo-compliant NFC performance.
Supply support for PN5190B1EV/C121Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global leader in secure connectivity solutions, specializing in high-performance NFC, RFID, and secure element technologies for automotive, industrial, and consumer applications.
The PN5190B1 product line delivers high-power, multi-protocol NFC frontends engineered for EMVCo Level 1 certification, ultra-low-power operation, and seamless integration into Linux/Android-based reader platforms.
FAQ
What is the pre-installed firmware version on PN5190B1EV/C121Y?
The PN5190B1EV/C121Y ships with firmware version 2.1 pre-programmed - the default version for volume production devices. This firmware supports encrypted firmware download, includes updated EEPROM settings for P2P target mode stability, and is validated for EMVCo L1 analog testing. Firmware updates to later versions (e.g., v2.7 or v2.9) are possible via secure command interface but require host-side implementation of the encrypted download protocol.
Does PN5190B1EV/C121Y support MIFARE Classic authentication in hardware?
Yes, the PN5190B1EV/C121Y includes a dedicated hardware crypto engine licensed for NXP MIFARE products, enabling full MIFARE Classic 1K/4K authentication and R/W operations without host CPU involvement. This hardware acceleration ensures deterministic timing, meets EMVCo L1 requirements, and prevents side-channel leakage - critical for payment terminals using MIFARE DESFire EV2 or Classic-based credentials.
Can PN5190B1EV/C121Y operate without an external 27.12 MHz crystal?
Yes, the PN5190B1EV/C121Y can operate without a 27.12 MHz crystal by configuring its internal PLL to accept 24 MHz, 32 MHz, or 48 MHz external clock inputs - specified via EEPROM register CLK_INPUT_FREQ (0012h). This eliminates crystal BOM cost and layout complexity while maintaining RF field accuracy and timing compliance for ISO/IEC 14443 and NFC-IP protocols.
What is the difference between LPCD and ULPCD modes on PN5190B1EV/C121Y?
LPCD (Low-Power Card Detection) draws ~45 μA and supports configurable polling intervals; ULPCD (Ultra-Low-Power Card Detection) draws just 22 μA average at 330 ms polling but disables the integrated DC-DC and restricts GPIO3 to abort-only function. ULPCD is intended for battery-critical applications like smart locks, while LPCD suits mains-powered terminals needing faster wake-up response.
Is the VFBGA64 package of PN5190B1EV/C121Y lead-free and RoHS compliant?
Yes, the PN5190B1EV/C121Y in VFBGA64 package (SOT1307-2) is lead-free and fully RoHS compliant, meeting EU Directive 2011/65/EU and JEDEC J-STD-020 moisture sensitivity level 3 (MSL=3). The package uses matte tin surface finish and is qualified for reflow soldering per IPC/JEDEC J-STD-020D.2 standards.
PN5190B1EV/C121Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 64-VFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- RFID Reader/Transponder
- Frequency:
- 13.56MHz
- Standards:
- FeliCa, ISO 14443, ISO 15693, ISO 18000-3, ISO 18092, ISO 21481, MIFARE, NFC
- Interface:
- SPI
- Voltage - Supply:
- 2.4V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VFBGA (4.5x4.5)
PN5190B1EV/C121Y FAQ
1.How can I place an order for PN5190B1EV/C121Y through Aetrix?
Please submit a Request for Quotation (RFQ) for PN5190B1EV/C121Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN5190B1EV/C121Y reliable?
The price and inventory of PN5190B1EV/C121Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN5190B1EV/C121Y is usually 5 days.
3.What payment methods are accepted for PN5190B1EV/C121Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN5190B1EV/C121Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN5190B1EV/C121Y?
PN5190B1EV/C121Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN5190B1EV/C121Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN5190B1EV/C121Y?
For technical support, including PN5190B1EV/C121Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN5190B1EV/C121Y requirements.
6.How does Aetrix verify that PN5190B1EV/C121Y is sourced from the original manufacturer or authorized distributors?
All PN5190B1EV/C121Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN5190B1EV/C121Y meets industry standards.
7.What is the process for return or replacement of PN5190B1EV/C121Y?
All PN5190B1EV/C121Y units undergo pre-shipment inspection (PSI). If there is an issue with PN5190B1EV/C121Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN5190B1EV/C121Y part is unused and in its original packaging.
Return procedure for PN5190B1EV/C121Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PN5190B1EV/C121Y Tags

-
SL2S2602FTBX
NXP Semiconductors

-
ST25DV04K-IER6S3
STMicroelectronics

-
ST25DV04K-IER6C3
STMicroelectronics

-
LXMSJZNCMD-217
Murata Electronics

-
NT3H2111W0FTTJ
NXP Semiconductors

-
NT3H2111W0FHKH
NXP Semiconductors

-
M24LR04E-RMC6T/2
STMicroelectronics

-
ST25DV04KC-JF6D3
STMicroelectronics

-
ST25DV64KC-IE6S3
STMicroelectronics
-
ST25DV64K-IER6T3
STMicroelectronics

-
NT3H2211W0FTTJ
NXP Semiconductors

-
NT3H2211W0FHKH
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
