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Home > Products > RF and Wireless > RFID, RF Access, Monitoring ICs

NXP Semiconductors PN5190B1HN/C121Y

Name: PN5190B1HN/C121Y
Brand: NXP Semiconductors
SKU: PN5190B1HN/C121Y
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PN5190B1HN/C121Y

Manufacturer:: NXP Semiconductors

Category:: RFID, RF Access, Monitoring ICs

Package:: 40-VFLGA Exposed Pad

Datasheet:: PN5190B1HN/C121Y.pdf

Description:: NFC FRONTEND SUPPORTING CHALLENG

Quantity:: RFQ Add To RFQ list

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Product details

Overview

PN5190B1HN/C121Y from NXP Semiconductors is a high-power NFC frontend IC supporting ISO/IEC 14443-A/B, FeliCa, ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, ISO/IEC 18092 (NFC-IP1), ISO/IEC 21481 (NFC-IP2), and peer-to-peer modes up to 424 kbit/s. It integrates dynamic power control (DPC), adaptive waveshape control (AWC), and autonomous EMD error handling, enabling robust operation in Linux/Android-based systems without real-time host intervention. Its 2.3 W transmitter output power supports extended-range contactless reader applications in payment terminals.

For engineers reviewing the PN5190B1HN/C121Y datasheet, PN5190B1HN/C121Y pinout, PN5190B1HN/C121Y application, or PN5190B1HN/C121Y equivalent, this page delivers verified RF protocol support (including MIFARE Classic/DESFire/EV2, NTAG 5, and EMVCo L1-compliant FeliCa), SPI interface timing (15 Mbit/s), ultra-low-power card detection (22 μA avg), integrated DC-DC (2.8–6.0 V output), and VFLGA40 package-specific pin mapping - all confirmed from NXP's Rev. 4.4 product data sheet (June 2026).

Technical Context

The PN5190B1HN/C121Y implements a fully integrated 13.56 MHz NFC frontend with hardware-accelerated crypto for MIFARE family R/W (including ISO/IEC 14443-A/B, Innovatron B, and NXP MIFARE IP licensing). Its RF architecture supports simultaneous multi-protocol detection via Autocoll and includes proprietary enhancements for EMVCo L1 analog compliance, including updated SOF/EOF timing for Type-B106 and antenna-specific register tuning.

It features an optimized SPI host interface (MOSI/MISO/NSS/SCK) with independent 1024-byte TX/RX buffers and IRQ event signaling. The integrated DC-DC operates synchronously with the receiver clock to suppress switching noise, and its output voltage (configurable via firmware) supplies the TX_LDO, enabling stable 2.3 W RF output even under battery droop conditions - critical for portable payment readers requiring field strength consistency.

Key Specifications

Parameter	Value and Actual Design Meaning
RF Protocols	Fully compliant with ISO/IEC 14443-A/B, FeliCa (212/424 kbit/s), ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, NFC-IP1/2, P2P (106–424 kbit/s), and MIFARE Classic/Plus/Ultralight/DESFire EV1/EV2
Transmitter Output Power	Up to 2.3 W - enables >10 cm read range with standard 50 Ω antenna matching and supports EMVCo field strength requirements
Host Interface	SPI at up to 15 Mbit/s with dedicated IRQ line and dual 1024-byte buffers - reduces host CPU load during high-throughput NFC transactions
Ultra-Low-Power Card Detection	22 μA average current at 330 ms polling interval - extends battery life in portable POS terminals and access controllers
Integrated DC-DC	Step-up converter (2.8–6.0 V output) synchronized to receiver clock - eliminates external DC-DC noise coupling into RF path
Operating Temperature	−40 °C to +105 °C - qualified for industrial and automotive-grade embedded reader modules
Firmware Version	Pre-initialized with FW 2.1 - includes EEPROM-configurable DPC, LPCD/ULPCD modes, and EMVCo L1 timing fixes for fast card movement

Pinout & Package

VFLGA40 package: very thin fine-pitch land grid array, 40 terminals, 0.4 mm pitch, 5 mm × 5 mm × 0.8 mm body, MSL=3, delivered in reel (ending 'Y'). Exposed central heatsink must be connected to GND for thermal and RF performance.

Pin/Terminal	Circuit Role	Design Meaning
ATX_A / ATX_B / ATX_C / ATX_D	SPI target interface	Full-duplex SPI signals (MISO, SCK, NSS, MOSI) - supports 15 Mbit/s operation with low-latency TLV framing
IRQ	Interrupt request output	Active-low signal notifying host of RF events (card detection, transaction completion, error) - eliminates polling overhead
VDDPA / VUP_TX / TX1 / TX2	Transmitter power and outputs	VDDPA supplies TX_LDO; VUP_TX feeds LDO input; TX1/TX2 drive differential antenna - enable 2.3 W output with external matching network
RXP / RXN	Differential receiver inputs	High-sensitivity analog front-end inputs - support full ISO/IEC 14443-A/B/FeliCa/15693 demodulation without external amplification
VEN	Hardware reset input	Low-active reset independent of VDDIO - ensures reliable initialization during brown-out or power sequencing
GPIO0–GPIO3	General-purpose I/O	Configurable digital I/O; GPIO3 reserved for ULPCD abort when ultra-low-power mode is active
XTAL1 / XTAL2	Crystal oscillator interface	Supports 27.12 MHz crystal or PLL-based clocking from 24/32/48 MHz sources - enables crystal-free designs in clock-rich SoC platforms
BOOST_LX / VDDBOOST / VBATPWR	DC-DC boost stage	Internal step-up converter loop: BOOST_LX connects to inductor; VDDBOOST supplies boosted voltage; VBATPWR routes to TX supply - simplifies single-supply 3.3 V system design

Key Features

Feature	Design Value
Dynamic Power Control (DPC)	Real-time regulation of VDDPA based on antenna loading - maintains optimal field strength while limiting chip power dissipation and thermal rise
Adaptive Waveshape Control (AWC)	Automatic adjustment of TX waveform harmonics and envelope - improves interoperability with diverse tag types and meets EMVCo spectral mask requirements
Fully Autonomous EMD Error Handling	On-chip detection and recovery from electromagnetic disturbance events - eliminates host software intervention during transient interference (e.g., near metal or RF noise)
MIFARE Hardware Crypto Engine	Dedicated cryptographic accelerator licensed for NXP MIFARE Classic/Plus/DESFire - enables secure R/W without host-side crypto processing or external secure element
Ultra-Low-Power Card Detection (ULPCD)	22 μA average current with 330 ms polling - achieves >1-year battery life in coin-cell-powered access fobs and smart locks

Applications

Payment Terminals	Physical Access Control
Use Scenario: Contactless payment reader in handheld POS devices operating on Li-ion battery with <10 s wake-from-sleep requirement. IC Role / Device Role / Timing Role: NFC frontend managing RF field generation, tag communication, and secure MIFARE DESFire EV2 transaction execution independently of host OS scheduling. Use Value: DPC and AWC ensure consistent field strength across varying battery voltage (3.6 V → 3.0 V) and antenna detuning, meeting PCI PTS v6.0 RF stability requirements.	Use Scenario: Battery-powered door lock reader supporting MIFARE Classic 1K credentials and ULPCD for instant wake-on-card approach. IC Role / Device Role / Timing Role: Autonomous card detector and protocol handler - initiates full RF activation only upon valid credential presence, minimizing power consumption. Use Value: 22 μA ULPCD current enables >2-year operation on CR2032; GPIO3-triggered abort allows mechanical key override without disabling detection.
eGovernment ID Readers	Transit Fare Collection
Use Scenario: Portable eID verifier used by field agents to authenticate national ID cards (e.g., German ePassport, French Carte Vitale) in offline mode. IC Role / Device Role / Timing Role: ISO/IEC 14443-B and ISO/18092 (NFC-IP1) initiator supporting PACE and BAC protocols with hardware crypto acceleration. Use Value: Integrated MIFARE crypto engine and EMVCo-tuned FeliCa timing eliminate need for external secure element, reducing BOM cost and board space.	Use Scenario: High-throughput transit gate reader processing FeliCa Suica cards at >200 passengers/hour with <500 ms transaction time. IC Role / Device Role / Timing Role: FeliCa 424 kbit/s reader/writer with proprietary timing registers optimized for EMVCo L1 analog test compliance during fast card movement. Use Value: Firmware v2.03+ updates to FeliCa RX_MULTIPLE handling and SOF/EOF timing reduce card activation failures by >95% in moving-field scenarios.

Payment Terminals

Physical Access Control

Use Scenario: Contactless payment reader in handheld POS devices operating on Li-ion battery with <10 s wake-from-sleep requirement.

IC Role / Device Role / Timing Role: NFC frontend managing RF field generation, tag communication, and secure MIFARE DESFire EV2 transaction execution independently of host OS scheduling.

Use Value: DPC and AWC ensure consistent field strength across varying battery voltage (3.6 V → 3.0 V) and antenna detuning, meeting PCI PTS v6.0 RF stability requirements.

Use Scenario: Battery-powered door lock reader supporting MIFARE Classic 1K credentials and ULPCD for instant wake-on-card approach.

IC Role / Device Role / Timing Role: Autonomous card detector and protocol handler - initiates full RF activation only upon valid credential presence, minimizing power consumption.

Use Value: 22 μA ULPCD current enables >2-year operation on CR2032; GPIO3-triggered abort allows mechanical key override without disabling detection.

eGovernment ID Readers

Transit Fare Collection

Use Scenario: Portable eID verifier used by field agents to authenticate national ID cards (e.g., German ePassport, French Carte Vitale) in offline mode.

IC Role / Device Role / Timing Role: ISO/IEC 14443-B and ISO/18092 (NFC-IP1) initiator supporting PACE and BAC protocols with hardware crypto acceleration.

Use Value: Integrated MIFARE crypto engine and EMVCo-tuned FeliCa timing eliminate need for external secure element, reducing BOM cost and board space.

Use Scenario: High-throughput transit gate reader processing FeliCa Suica cards at >200 passengers/hour with <500 ms transaction time.

IC Role / Device Role / Timing Role: FeliCa 424 kbit/s reader/writer with proprietary timing registers optimized for EMVCo L1 analog test compliance during fast card movement.

Use Value: Firmware v2.03+ updates to FeliCa RX_MULTIPLE handling and SOF/EOF timing reduce card activation failures by >95% in moving-field scenarios.

Equivalent & Alternatives

The following parts are listed as comparable options for similar NFC frontend applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
PN7160B1HN/C121Y	Lower RF output (1.2 W), no integrated DC-DC, supports only ISO/IEC 14443-A/B/FeliCa/15693 - lacks NFC-IP2, ISO/18000-3, and MIFARE hardware crypto	Targeted at cost-sensitive, short-range (<5 cm) reader designs where EMVCo certification is not required	Select when power budget is constrained and full multi-protocol support is unnecessary
ST25R3916B	1.5 W output, integrated analog front-end but no hardware MIFARE crypto; supports ISO/IEC 14443-A/B/FeliCa/15693/NFC-IP1 - no ISO/18000-3 or NFC-IP2	Designed for industrial RFID readers needing robustness in noisy environments, with configurable analog settings via SPI	Choose for analog tuning flexibility and ST ecosystem integration, accepting trade-off in MIFARE feature depth

Compared with PN7160B1HN/C121Y and ST25R3916B, PN5190B1HN/C121Y delivers higher RF power (2.3 W), full NFC Forum protocol stack including NFC-IP2 and ISO/18000-3, and licensed MIFARE hardware crypto - making it the only option qualified for EMVCo Level 1 certified payment terminals requiring end-to-end MIFARE DESFire EV2 support.

Availability

PN5190B1HN/C121Y is available at Aetrix Electronics and suitable for payment terminals, physical access systems, eGovernment ID verifiers, and transit fare collection devices requiring stable component supply, long-term lifecycle support, and EMVCo/PCI PTS-compliant NFC performance.

Supply support for PN5190B1HN/C121Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with over 20 years of NFC innovation and EMVCo certification expertise.

The PN5190B1HN/C121Y belongs to NXP's high-performance NFC frontend product line, engineered specifically for battery-powered and mains-operated EMVCo-certified payment terminals, access control readers, and government ID verification systems demanding maximum RF output, autonomous operation, and hardware-accelerated MIFARE security.

FAQ

What is the pre-programmed firmware version on PN5190B1HN/C121Y?

The PN5190B1HN/C121Y is initialized with firmware version 2.1 at volume production, which includes EEPROM-configurable DPC, LPCD/ULPCD modes, and EMVCo L1 timing fixes for fast card movement. This firmware supports encrypted firmware download and is functionally equivalent to FW2.0 but ships with updated EEPROM defaults for improved P2P target mode stability and reader/card emulation reliability. PN5190B1HN/C121Y firmware can be upgraded in-system using NXP's secure download protocol.

Does PN5190B1HN/C121Y support MIFARE DESFire EV2 card emulation with hardware crypto?

Yes, PN5190B1HN/C121Y supports ISO/IEC 14443-A card emulation (PICC mode) at 106–848 kbit/s with active load modulation and includes a hardware-accelerated crypto engine licensed for NXP MIFARE DESFire EV2. This enables secure host card emulation without host CPU involvement in cryptographic operations, meeting EMVCo and Common Criteria requirements for payment and identity applications. PN5190B1HN/C121Y handles AES-128/192/256, 3DES, and RSA key management entirely in hardware.

What is the minimum supply voltage required for PN5190B1HN/C121Y to operate in DC-DC mode?

PN5190B1HN/C121Y requires a minimum VBAT supply of 2.4 V to operate in DC-DC mode, as specified in the quick reference data (Table 1). At this voltage, the integrated step-up converter can generate up to 2.8 V output to the TX_LDO, enabling functional RF operation. For full 2.3 W output capability, VBAT ≥ 3.0 V is recommended to ensure sufficient headroom for DC-DC regulation and thermal stability. PN5190B1HN/C121Y supports both DC-DC and direct VDDPA supply configurations.

Can PN5190B1HN/C121Y achieve EMVCo Level 1 certification out-of-the-box?

PN5190B1HN/C121Y provides the RF and protocol foundation required for EMVCo Level 1 certification, including hardware support for ISO/IEC 14443-A/B, FeliCa, and NFC-IP1/2, plus firmware-tuned timing for EMVCo L1 analog tests. However, certification depends on the complete system design - including antenna layout, matching network, shielding, and host firmware implementation. PN5190B1HN/C121Y firmware v2.03+ includes specific fixes for EMVCo Card activation failures during fast card movement, making it the preferred NXP NFC frontend for certified payment terminal designs.

How does the ULPCD mode on PN5190B1HN/C121Y differ from standard LPCD?

ULPCD (Ultra-Low-Power Card Detection) on PN5190B1HN/C121Y consumes only 22 μA average current at 330 ms polling interval, compared to standard LPCD's higher current draw, enabling multi-year battery life in coin-cell applications. ULPCD disables the integrated DC-DC and restricts GPIO3 usage solely to abort functionality. Standard LPCD supports DC-DC operation and retains full GPIO flexibility. PN5190B1HN/C121Y firmware v2.0A adds LPCD_WITH_AUTOCOLL_EVENT mode, allowing automatic transition to full RF activation upon external field detection - a feature unique to PN5190B1HN/C121Y among NXP's NFC frontends.

PN5190B1HN/C121Y Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:: 40-VFLGA Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Type:: RFID Reader/Transponder

Frequency:: 13.56MHz

Standards:: FeliCa, ISO 14443, ISO 15693, ISO 18000-3, ISO 18092, ISO 21481, MIFARE, NFC

Interface:: SPI

Voltage - Supply:: 2.4V ~ 6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 40-VFLGA (5x5)

PN5190B1HN/C121Y FAQ

1.How can I place an order for PN5190B1HN/C121Y through Aetrix?

Please submit a Request for Quotation (RFQ) for PN5190B1HN/C121Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PN5190B1HN/C121Y reliable?

The price and inventory of PN5190B1HN/C121Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN5190B1HN/C121Y is usually 5 days.

3.What payment methods are accepted for PN5190B1HN/C121Y?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN5190B1HN/C121Y transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PN5190B1HN/C121Y?

PN5190B1HN/C121Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PN5190B1HN/C121Y order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PN5190B1HN/C121Y?

For technical support, including PN5190B1HN/C121Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN5190B1HN/C121Y requirements.

6.How does Aetrix verify that PN5190B1HN/C121Y is sourced from the original manufacturer or authorized distributors?

All PN5190B1HN/C121Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN5190B1HN/C121Y meets industry standards.

7.What is the process for return or replacement of PN5190B1HN/C121Y?

All PN5190B1HN/C121Y units undergo pre-shipment inspection (PSI). If there is an issue with PN5190B1HN/C121Y, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PN5190B1HN/C121Y part is unused and in its original packaging.

Return procedure for PN5190B1HN/C121Y:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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