NXP Semiconductors PN5190B1HN/C127K
- Part No.:
- PN5190B1HN/C127K
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 40-VFLGA Exposed Pad
- Datasheet:
-
PN5190B1HN/C127K.pdf
- Description:
- PN5190B1HN/C127K
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PN5190B1HN/C127K from NXP Semiconductors is a high-power NFC frontend IC supporting ISO/IEC 14443-A/B, FeliCa, ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, ISO/IEC 18092 (NFC-IP1), and ISO/IEC 21481 (NFC-IP2) protocols at 13.56 MHz. It delivers up to 2.3 W RF output power with integrated DC-DC and TX_LDO, operates from 2.4–5.5 V supply, and features dynamic power control (DPC), adaptive waveshape control (AWC), and autonomous EMD error handling - enabling robust NFC reader functionality in Linux/Android-based payment terminals and access systems.
For engineers reviewing the PN5190B1HN/C127K datasheet, PN5190B1HN/C127K pinout, PN5190B1HN/C127K application, or PN5190B1HN/C127K equivalent, this page provides verified technical context, firmware version 2.7-specific behavior, VFLGA40 package mapping, SPI host interface details, and real-world design implications for EMVCo-compliant reader design, ultra-low-power card detection (ULPCD), and autonomous mode operation.
Technical Context
The PN5190B1HN/C127K implements a fully integrated 13.56 MHz NFC frontend with independent TX/RX buffers (1024 bytes each), SPI interface up to 15 Mbit/s, and hardware-accelerated cryptographic support for MIFARE Classic, Plus, DESFire, and Ultralight cards. Its RF architecture includes dual antenna outputs (TX1/TX2), differential receiver inputs (RXP/RXN), and VMID symmetry point connection for balanced antenna matching.
Firmware version 2.7 enables ULPCD with 22 μA average current, supports LPCD_WITH_AUTOCOLL_EVENT (0x13), introduces DYNAMIC_POWERLEVEL_REG (0x64), and deprecates P2P active target mode. The integrated DC-DC (2.8–6.0 V output) is synchronized with receiver clock to suppress switching noise, and its usage is mandatory for ULPCD but prohibited for ultra-low-power card detection (ULPCD) scenarios requiring GPIO3 abort functionality.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Protocols | Fully compliant with ISO/IEC 14443-A/B, FeliCa (212/424 kbit/s), ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, NFC-IP1/2, and all NFC tag types (1–5) |
| Transmit Power | Up to 2.3 W output - enables extended read range (>10 cm) for MIFARE DESFire EV2 and NTAG 5 in battery-constrained handheld readers |
| Supply Voltage | VDD(VBAT): 2.4–5.5 V; VDDIO: 2.4–3.6 V - supports single-supply 3.3 V system design with integrated DC-DC boosting VDDPA to 6.0 V |
| Power Consumption | IULPCD = 22 μA (typical); Istb = 45–110 μA - enables multi-week battery life in portable access control devices using ULPCD polling |
| SPI Interface | 15 Mbit/s max rate with MOSI/MISO/NSS/SCK + IRQ line - reduces host CPU load during high-throughput card emulation and P2P exchange |
| Firmware Version | Pre-programmed FW 2.7 - includes DPC_GUARD_TIME default 0xFF, LFO_TRIM_CALIBRATION (0xCED), and LPCD_WITH_AUTOCOLL_EVENT support |
| Operating Temp | −40 °C to +105 °C (TX current = 120 mA @ VDDPA = 3.6 V) - qualified for industrial-grade embedded terminals and outdoor kiosks |
Pinout & Package
VFLGA40 package: very thin fine-pitch land grid array, 40 terminals, 0.4 mm pitch, 5 mm × 5 mm × 0.8 mm body, MSL=3, delivered in multiple trays (K suffix). Thermal pad on underside must be connected to PCB ground for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ATX_A / ATX_B / ATX_C / ATX_D | SPI target interface | Full-duplex 15 Mbit/s SPI data I/O with dedicated NSS and clock - requires pull-up on ATX_C for proper target selection |
| IRQ | Interrupt request output | Active-low event signal (e.g., card detected, RF exchange complete) - enables low-latency host response without polling |
| VDDPA / VUP_TX / TX1 / TX2 | Transmitter power and drive | VDDPA supplies TX_LDO (up to 6.0 V); TX1/TX2 drive differential antenna - requires external matching network and 10 µF/4.7 µF bulk caps |
| RXP / RXN | Differential RF input | High-sensitivity receiver inputs - require 100 pF AC coupling and symmetric trace routing to minimize common-mode noise |
| VMID | Antenna symmetry reference | Connects to antenna center tap or ground via 100 nF capacitor - critical for balanced field generation and EMI reduction |
| GPIO0–GPIO3 | Configurable I/O | GPIO3 reserved exclusively for ULPCD abort; others support wake-up, status indication, or external DC-DC control per FW 2.03+ updates |
| VEN | Hardware reset | Low-active reset independent of VDDIO - must be debounced externally to prevent spurious resets during power ramp |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic Power Control (DPC) 2.0 | Real-time regulation of VDDPA based on antenna loading - maintains stable field strength while reducing chip junction temperature by up to 25 °C |
| Adaptive Waveshape Control (AWC) | Automatic adjustment of TX waveform harmonics - ensures EMVCo L1 analog compliance without host intervention or calibration tables |
| Ultra-Low-Power Card Detection (ULPCD) | 22 μA typical current with 330 ms polling interval - enables >6-month battery life in Bluetooth/NFC combo access fobs |
| Autonomous EMD Error Handling | Fully hardware-managed electromagnetic disturbance recovery - eliminates host firmware complexity for field collapse or metal interference events |
| Integrated DC-DC with Synchronized Clock | Step-up converter (2.8–6.0 V) clocked from receiver domain - avoids spectral contamination in 13.56 MHz band and improves SNR by 8 dB |
Applications
| Payment Terminals | Physical Access Control |
|---|---|
Use Scenario: Contactless EMVCo-certified payment terminals processing MIFARE DESFire EV2 and NTAG 5 transactions in retail environments. IC Role / Device Role / Timing Role: NFC frontend managing RF field generation, protocol stack offload, and secure crypto acceleration for host MCU. Use Value: 2.3 W output enables >8 cm read range on thick wallets; FW 2.7's improved SOF/EOF timing passes EMVCo L1 analog test without manual tuning. |
Use Scenario: Battery-powered door readers supporting MIFARE Classic 1K and FeliCa credentials in office buildings. IC Role / Device Role / Timing Role: Autonomous NFC reader executing card detection, authentication, and credential validation without host CPU involvement. Use Value: ULPCD at 22 μA extends CR2450 battery life to 18 months; GPIO3 abort allows instant wake-from-standby on card approach. |
| e-Government ID Readers | Industrial Asset Tagging |
Use Scenario: Portable ePassport and national ID readers used by border control agents in field deployments. IC Role / Device Role / Timing Role: High-reliability NFC frontend supporting ISO/IEC 14443-B and ISO/IEC 18000-3 Mode 3 for legacy and modern e-documents. Use Value: Dual-mode (reader/card emulation) with 848 kbit/s speed ensures sub-500 ms biometric data transfer; −40 °C to +105 °C rating guarantees operation in extreme climates. |
Use Scenario: Ruggedized handheld scanners reading ISO/IEC 15693 ICODE tags on machinery in factory floors. IC Role / Device Role / Timing Role: Industrial-grade NFC reader with robust ESD protection and metal-tolerant antenna tuning via VMID feedback. Use Value: Integrated DC-DC sustains 2.0 W output even as battery voltage drops to 2.4 V; AWC compensates for field distortion near steel enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC frontend applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7160B1HN/C127K | Lower RF output (1.2 W), no integrated DC-DC, FW 2.7 compatible but lacks DPC and AWC | Targeted at cost-sensitive, short-range (<5 cm) readers where thermal headroom is not constrained | Select when ULPCD and autonomous EMD handling are not required and board space permits external boost converter |
| PN5180A1HN/C127K | Same VFLGA40 package, FW 2.7, but limited to ISO/IEC 14443-A/B/FeliCa - excludes ISO/IEC 15693 and NFC-IP2 | Suitable for MIFARE-only infrastructure where ISO/IEC 18000-3 or NTAG 5 support is unnecessary | Choose when interoperability with legacy ICODE or FeliCa-only systems suffices and 2.3 W output is excessive |
Compared with PN7160B1HN/C127K and PN5180A1HN/C127K, the PN5190B1HN/C127K uniquely delivers full NFC Forum protocol coverage, 2.3 W output with thermal-aware DPC, and ULPCD at 22 μA - making it the only option for EMVCo-certified handhelds requiring simultaneous MIFARE, FeliCa, and NTAG 5 support under battery and thermal constraints.
Availability
PN5190B1HN/C127K is available at Aetrix Electronics and suitable for payment terminals, physical access control systems, and e-government ID readers requiring stable component supply, long-term lifecycle assurance, and firmware version 2.7 pre-programming.
Supply support for PN5190B1HN/C127K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with over 20 years of NFC innovation and EMVCo certification expertise.
The PN5190B1 product line targets high-reliability, battery-operated NFC reader systems demanding full protocol coverage, autonomous operation, and thermal-efficient RF performance - designed specifically for next-generation payment, access, and identity verification platforms.
FAQ
What firmware version is pre-programmed on PN5190B1HN/C127K?
The PN5190B1HN/C127K ships with firmware version 2.7 pre-installed. This version includes critical enhancements for EMVCo L1 analog compliance (improved SOF/EOF timing), ULPCD support with GPIO3 abort capability, and the DYNAMIC_POWERLEVEL_REG (0x64) for runtime DPC adjustment. Firmware updates beyond 2.7 are supported via encrypted download, but downgrading to versions below 2.7 is not permitted per NXP's security policy.
Can PN5190B1HN/C127K operate without the integrated DC-DC?
Yes, the PN5190B1HN/C127K can operate without the integrated DC-DC by supplying VDDPA directly from an external 3.3–6.0 V source. However, doing so forfeits dynamic power control and thermal optimization - the chip will draw up to 400 mA at VDDPA and dissipate significantly more heat. For ULPCD operation, the DC-DC must be disabled, but for all other modes (especially high-power reader or card emulation), using the integrated DC-DC is strongly recommended to maintain RF stability and junction temperature below 125 °C.
What is the function of the VMID pin on PN5190B1HN/C127K?
The VMID pin on PN5190B1HN/C127K serves as the electrical symmetry reference point for the NFC antenna circuit. It must be connected to the antenna's center tap or ground plane via a 100 nF blocking capacitor. Proper VMID connection ensures balanced differential drive across TX1/TX2, minimizes common-mode emissions, and improves field uniformity - directly impacting EMVCo radiated emission test margins and read reliability near metallic surfaces.
Does PN5190B1HN/C127K support host card emulation (HCE) with Android?
Yes, the PN5190B1HN/C127K supports ISO/IEC 14443-A card emulation mode at data rates up to 848 kbit/s with active load modulation, enabling extended communication range for Android HCE implementations. It handles low-level RF framing and modulation autonomously, allowing the host Android system to focus on application-layer logic. However, full HCE stack integration requires NXP's proprietary software libraries and Android HAL extensions - not provided with the PN5190B1HN/C127K hardware alone.
How does GPIO3 function in ultra-low-power card detection (ULPCD) mode on PN5190B1HN/C127K?
In ULPCD mode, GPIO3 on PN5190B1HN/C127K is hardwired to serve exclusively as an abort signal - it cannot be repurposed for general I/O. When an external RF field is detected during ULPCD polling, asserting GPIO3 low forces immediate exit from ULPCD and triggers an autocoll event, waking the host controller. This dedicated function ensures deterministic, sub-100 µs wake-up latency critical for battery-powered access fobs and wearables.
PN5190B1HN/C127K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 40-VFLGA Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- RFID Reader/Transponder
- Frequency:
- 13.56MHz
- Standards:
- FeliCa, ISO 14443-A, ISO 14443-B, ISO 15693, ISO 18000-3, ISO 18092, ISO 21481, Mifare, NFC
- Interface:
- I2C, SPI, USB
- Voltage - Supply:
- 2.4V ~ 5.5V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-VFLGA (5x5)
PN5190B1HN/C127K FAQ
1.How can I place an order for PN5190B1HN/C127K through Aetrix?
Please submit a Request for Quotation (RFQ) for PN5190B1HN/C127K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN5190B1HN/C127K reliable?
The price and inventory of PN5190B1HN/C127K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN5190B1HN/C127K is usually 5 days.
3.What payment methods are accepted for PN5190B1HN/C127K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN5190B1HN/C127K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN5190B1HN/C127K?
PN5190B1HN/C127K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN5190B1HN/C127K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN5190B1HN/C127K?
For technical support, including PN5190B1HN/C127K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN5190B1HN/C127K requirements.
6.How does Aetrix verify that PN5190B1HN/C127K is sourced from the original manufacturer or authorized distributors?
All PN5190B1HN/C127K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN5190B1HN/C127K meets industry standards.
7.What is the process for return or replacement of PN5190B1HN/C127K?
All PN5190B1HN/C127K units undergo pre-shipment inspection (PSI). If there is an issue with PN5190B1HN/C127K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN5190B1HN/C127K part is unused and in its original packaging.
Return procedure for PN5190B1HN/C127K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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