NXP Semiconductors PN5190B2EV/C130K

Overview

PN5190B2EV/C130K from NXP Semiconductors is a high-power NFC frontend IC supporting ISO/IEC 14443-A/B, FeliCa, ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, ISO/IEC 18092 (NFC-IP1), ISO/IEC 21481 (NFC-IP2), and peer-to-peer modes up to 424 kbit/s. It integrates dynamic power control (DPC), adaptive waveshape control (AWC), and ultra-low-power card detection (ULPCD) with 22 μA average current. It operates from 2.4–5.5 V supply and delivers up to 2.3 W RF output power - enabling secure contactless payment terminals and access control readers.

For engineers reviewing the PN5190B2EV/C130K datasheet, PN5190B2EV/C130K pinout, PN5190B2EV/C130K application, or PN5190B2EV/C130K equivalent, key selection considerations include its VFBGA64 package (4.5 mm × 4.5 mm × 0.80 mm), SPI host interface (15 Mbit/s), integrated DC-DC boost (2.8–6.0 V), and firmware version 3.0 preloaded for encrypted download.

Technical Context

The PN5190B2EV/C130K implements a fully integrated 13.56 MHz NFC frontend with autonomous real-time signal processing: DPC2.0 uses true transmitter current measurement for sub-1 ms regulation without host intervention, while AWC dynamically adjusts antenna driver waveforms to maintain compliance under detuning. Its receiver employs automatic RF input attenuation and true baseband amplification for robust tag/card/mobile phone communication.

It supports dual low-power detection modes - software-based LPCD (max range) and hardware-based ULPCD (22 μA avg) - with GPIO3 dedicated to ULPCD abort. The integrated DC-DC is synchronized to the receiver clock to suppress noise, and the TX_LDO provides 100 mV granularity voltage control for precise DPC implementation.

Key Specifications

Pinout & Package

VFBGA64 package: plastic very thin fine-pitch ball grid array, 64 balls, 4.5 mm × 4.5 mm × 0.80 mm body, MSL=3, delivered in trays.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NFC frontend applications.

Compared with PN5180B2HN/C130K and PN7150B0HN/C130K, the PN5190B2EV/C130K uniquely combines 2.3 W RF output, ULPCD (22 μA), integrated DC-DC, and full NFC Forum/EMVCo protocol support - making it the only option for battery-powered, high-range, certified payment terminals.

Availability

PN5190B2EV/C130K is available at Aetrix Electronics and suitable for payment terminals, physical access systems, and e-government ID readers requiring stable component supply, long-term lifecycle assurance, and MSL3-compliant packaging for automated assembly.

Supply support for PN5190B2EV/C130K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.

The PN5190B2EV/C130K belongs to NXP's high-performance NFC frontend product line, engineered specifically for EMVCo-certified contactless payment terminals and industrial-grade access control systems demanding ultra-low-power operation and robust RF performance.

FAQ

What firmware version is preloaded on PN5190B2EV/C130K?

The PN5190B2EV/C130K ships with firmware version 3.0 preloaded, supporting encrypted firmware download via HDLL commands. This version is functionally identical to FW 2.06 except for enhanced security in the firmware update mechanism and cannot be downgraded to earlier versions. Firmware updates must be performed using NXP's official tools and signed images to maintain cryptographic integrity.

Does PN5190B2EV/C130K support FeliCa without external crypto acceleration?

Yes, PN5190B2EV/C130K supports FeliCa at 212 kbit/s and 424 kbit/s in reader/writer mode without requiring external crypto acceleration. However, cryptographic operations for FeliCa authentication are handled by the host controller - the PN5190B2EV/C130K provides only the RF layer and protocol framing. Its integrated crypto engine is licensed exclusively for NXP MIFARE products and ISO/IEC 14443-A/B.

Can PN5190B2EV/C130K operate with a 24 MHz external clock instead of a 27.12 MHz crystal?

Yes, PN5190B2EV/C130K can use a 24 MHz, 32 MHz, or 48 MHz external clock source instead of a 27.12 MHz crystal by configuring the CLK_INPUT_FREQ register (0012h) in EEPROM. The internal PLL generates the precise 27.12 MHz RF carrier and system clocks. This flexibility eliminates the need for a dedicated 27.12 MHz crystal, reducing BOM count and PCB area in systems already running one of these standard clock frequencies.

What is the purpose of the PRD1 and PRD2 pins on PN5190B2EV/C130K?

The PRD1 and PRD2 pins on PN5190B2EV/C130K implement package removal detection - they form an internal conductive loop that triggers a security alert if the IC package is physically tampered with or removed from the PCB. When activated, this feature invalidates sensitive keys stored in non-volatile memory and halts secure operations. It is required for EMVCo Level 2 certification in payment terminals and meets common criteria for tamper-evident design in government ID readers.

How does the ULPCD mode affect GPIO3 functionality on PN5190B2EV/C130K?

When ULPCD mode is enabled on PN5190B2EV/C130K, GPIO3 is exclusively reserved for aborting the ULPCD state and cannot be used for any other general-purpose I/O function. This hardware-enforced restriction ensures deterministic wake-up behavior and prevents software conflicts that could compromise low-power operation. If GPIO3 is needed for alternate functions, ULPCD must be disabled in favor of standard LPCD mode, which uses software-based detection and frees GPIO3 for general use.