NXP Semiconductors PN5190B2HN/C130Y

Overview

PN5190B2HN/C130Y from NXP Semiconductors is a high-power NFC frontend IC supporting ISO/IEC 14443-A/B, FeliCa, MIFARE Classic/Plus/Ultralight/DESFire, ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, NFC-IP1/2, and peer-to-peer modes up to 424 kbit/s. It integrates dynamic power control (DPC), adaptive waveshape control (AWC), and ultra-low-power card detection (ULPCD) with 22 µA average current. Designed for secure payment terminals and access control readers requiring robust RF performance under antenna detuning.

For engineers reviewing the PN5190B2HN/C130Y datasheet, PN5190B2HN/C130Y pinout, PN5190B2HN/C130Y application, or PN5190B2HN/C130Y equivalent, key selection considerations include integrated DC-DC support (up to 6.0 V TX supply), SPI interface at 15 Mbit/s, 40-pin VFLGA package, ULPCD current consumption ≤22 µA, and hardware-accelerated MIFARE crypto operations compliant with NXP's IP licensing rights.

Technical Context

The PN5190B2HN/C130Y implements a fully integrated 13.56 MHz NFC frontend with autonomous DPC2.0 using true transmitter current measurement and sub-1 ms regulation response. Its receiver chain includes automatic RF input attenuation and a true baseband amplifier (BBA) for extended communication range with tags and mobile phones.

It supports dual clocking: external 27.12 MHz crystal or PLL-synchronized 24/32/48 MHz reference; integrates a step-up DC-DC converter (2.8–6.0 V output) synchronized with receiver clock to suppress noise; and provides dedicated TX_LDO with 100 mV granularity for precise DPC voltage control independent of host intervention.

Key Specifications

Pinout & Package

VFLGA40 package: very thin fine-pitch land grid array, 40 terminals, 0.4 mm pitch, 5 mm × 5 mm × 0.8 mm body, MSL=3, delivered in reel (ending 'Y'). Exposed thermal pad connected to GND for thermal management.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar NFC frontend applications.

Compared with PN7160B0HN/C130Y and ST25R3916B, PN5190B2HN/C130Y uniquely combines EMVCo-compliant high-power transmission, autonomous DPC2.0, hardware ULPCD, and full MIFARE crypto licensing - making it the only option for battery-powered, security-certified payment and access systems demanding zero host intervention during critical RF operations.

Availability

PN5190B2HN/C130Y is available at Aetrix Electronics and suitable for payment terminals, physical access readers, and e-government ID verification systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for regulated deployments.

Supply support for PN5190B2HN/C130Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global leader in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in NFC, RFID, and secure element technologies.

The PN5190B2HN/C130Y belongs to NXP's high-performance NFC frontend product line, engineered specifically for EMVCo-certified payment terminals and battery-operated access control systems requiring autonomous RF regulation, ultra-low-power wake-up, and hardware-accelerated MIFARE operations.

FAQ

What is the primary function of the PN5190B2HN/C130Y in an NFC system?

The PN5190B2HN/C130Y serves as a complete NFC frontend IC, handling all RF layer functions including antenna driving, signal demodulation, protocol encoding/decoding for ISO/IEC 14443-A/B/FeliCa/15693/18000-3/NFC-IP1/2, and hardware-accelerated MIFARE crypto operations. It operates autonomously with features like DPC2.0 and ULPCD, reducing host controller involvement in timing-critical tasks. The PN5190B2HN/C130Y enables certified payment and secure access applications without requiring host-side RF processing.

Does the PN5190B2HN/C130Y support both reader and card emulation modes?

Yes, the PN5190B2HN/C130Y supports full reader/writer mode across all major protocols (ISO/IEC 14443-A/B, FeliCa, ISO/IEC 15693, etc.) and ISO/IEC 14443-A card emulation (PICC) mode at data rates from 106 kbit/s to 848 kbit/s with active load modulation. This allows it to emulate MIFARE Classic, DESFire, and other contactless smart cards while maintaining extended communication range. The PN5190B2HN/C130Y implements this using dedicated analog circuitry and hardware modulation control - no host CPU cycles are consumed during emulation.

What firmware version ships with the PN5190B2HN/C130Y, and can it be updated?

The PN5190B2HN/C130Y ships pre-initialized with firmware version 3.0, which supports encrypted firmware download via HDLL commands for enhanced security. Firmware updates are possible using the CTS_FAST_CONFIGURE command (0x2B) and other secure mechanisms defined in the datasheet. Downgrading to earlier versions is not permitted. All firmware revisions (3.02–3.07) maintain backward compatibility and introduce improvements such as DPR, LFO calibration, and LPCD-with-Autocoll event mode. The PN5190B2HN/C130Y firmware is stored in secure flash and protected against unauthorized modification.

How does the integrated DC-DC converter benefit system design?

The integrated DC-DC converter in the PN5190B2HN/C130Y is a synchronized step-up regulator delivering 2.8–6.0 V to the transmitter stage, enabling maximum RF output power from a single 3.3 V supply. It eliminates external DC-DC components, reduces board space, and avoids noise coupling by synchronizing its clock with the receiver path. When used with DPC2.0, it dynamically adjusts output voltage to minimize chip power dissipation during antenna loading - critical for thermal management in compact enclosures. The PN5190B2HN/C130Y allows optional use of the DC-DC: it is required for ULPCD but disabled in ultra-low-power card detection (ULPCD) mode.

What are the key differences between LPCD and ULPCD modes on the PN5190B2HN/C130Y?

LPCD (low-power card detection) uses software-based I/Q channel analysis for maximum detection range but consumes more current (~45 µA standby). ULPCD (ultra-low-power card detection) is hardware-accelerated and uses amplitude-only sensing, achieving ≤22 µA average current at 330 ms polling intervals - ideal for multi-year battery operation. ULPCD disables GPIO3 for any other function and requires the DC-DC to be inactive. Both modes generate IRQ events to wake the host upon card detection. The PN5190B2HN/C130Y supports seamless transition from ULPCD to full reader mode within milliseconds, preserving system responsiveness.