NXP Semiconductors PN5321A3HN/C106518
- Part No.:
- PN5321A3HN/C106518
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
PN5321A3HN/C106518.pdf
- Description:
- NFC INTEGRATED SOLUTION
- Quantity:
- Payment:

- Shipping:

Inventory:3,352
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PN5321A3HN/C106518 from NXP Semiconductors is a Near Field Communication (NFC) controller IC built on an 80C51 microcontroller core, supporting ISO/IEC 14443A/MIFARE, FeliCa, ISO/IEC 14443B (Reader/Writer), and NFCIP-1 (ISO/IEC 18092) protocols. It delivers up to 424 kbit/s bidirectional data rates, integrates a 40 KB ROM and 1 KB RAM, and operates from 2.7–5.5 V with Hard-Power-Down current as low as 1 µA. It enables secure mobile payment, access control, and peer-to-peer data exchange in portable devices.
For engineers reviewing the PN5321A3HN/C106518 datasheet, PN5321A3HN/C106518 pinout, PN5321A3HN/C106518 application, or PN5321A3HN/C106518 equivalent, key selection considerations include its 6 operating modes (Reader/Writer, Card Emulation, P2P), integrated RF level and data mode detectors, support for MIFARE Classic 1K/4K encryption, 50 mm typical read range (Reader mode), and compatibility with SPI/I²C/HSU host interfaces.
Technical Context
The PN5321A3HN/C106518 implements a full-contactless interface unit (CIU) with dedicated hardware acceleration for ISO/IEC 14443A framing, CRC-16, parity generation/check, and Manchester/Modified Miller/BPSK modulation decoding. Its analog front-end includes buffered TX drivers, integrated RF level detection, and antenna presence sensing - enabling direct connection to external antennas without active components.
It supports dual-role operation: as a Reader/Writer handling anticollision (firmware-implemented for Type B), and as a card emulator responding via load modulation (internal transmitter or LOADMOD pin). The CIU's 64-byte FIFO, programmable timers, and NFC-WI/S2C interface for secure IC co-processing enable robust, low-latency NFC stack implementation in resource-constrained embedded systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Frequency | 13.56 MHz carrier - defines RF interface compliance with global NFC standards (ISO/IEC 14443, FeliCa, NFCIP-1). |
| Max Data Rate | 424 kbit/s bidirectional - enables high-speed P2P file transfer and fast MIFARE/FeliCa transaction completion. |
| Digital Supply Voltage | 2.7–5.5 V - allows direct battery connection (e.g., single Li-ion or 3×AA) without external LDO for DVDD/AVDD/TVDD. |
| Hard-Power-Down Current | 1 µA typical - extends battery life in always-on NFC-enabled wearables and IoT tags. |
| Operating Temperature | −30 °C to +85 °C - ensures reliability in automotive infotainment, industrial handhelds, and outdoor access terminals. |
| Host Interfaces | SPI, I²C, High-Speed UART - provides flexible integration with MCU hosts ranging from Cortex-M0+ to application processors. |
| ROM/RAM | 40 KB ROM / 1 KB RAM - hosts firmware for protocol stacks (MIFARE, FeliCa, NFCIP-1) and runtime variables without external memory. |
Pinout & Package
HVQFN40 package (6 × 6 × 0.85 mm, leadless, SOT618-1, MSL Level 2) with exposed thermal pad for efficient heat dissipation in compact NFC modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VSS | Ground reference | Common return path for digital, analog, and RF sections; requires low-impedance PCB plane connection. |
| VBAT | Main power input | Supplies internal LDO; must be stable 2.7–5.5 V; powers DVDD, AVDD, TVDD, PVDD, SVDD simultaneously. |
| IRQ | Interrupt request output | Active-low signal alerts host of event completion (e.g., frame received, command executed); supports wake-up from Power-down. |
| RSTPD_N | Reset/power-down control | Active-low input resets device or forces Hard-Power-Down mode; debounced internally for reliable state transition. |
| LOADMOD | External load modulation driver | Drives external active circuit for enhanced card emulation range; bypasses internal TX for optimized field shaping. |
| SIGIN/SIGOUT | Analog RF interface | Direct connection points for external analog front-end enabling >424 kbit/s operation (e.g., 3.39 Mbit/s). |
| NSS/MOSI/MISO/SCK | SPI interface signals | Enable high-speed synchronous communication with host MCU; NSS supports multi-slave configurations. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated RF level detector | Enables automatic RF field detection for NFCIP-1 initiator activation and collision avoidance without host polling. |
| 64-byte send/receive FIFO | Reduces host CPU overhead during burst transfers (e.g., MIFARE sector reads) and prevents frame loss at 424 kbit/s. |
| Antenna presence detector | Validates antenna integrity during production test and runtime; eliminates field-tuning uncertainty in mass manufacturing. |
| Power switch for secure IC | Provides controlled SVDD output (DVDD −0.5 V to DVDD) to power external secure element (e.g., A700x, SLB9670) via NFC-WI/S2C. |
| Low-power modes | Hard-Power-Down (1 µA) and Soft-Power-Down (22 µA) with auto-wake on SPI/I²C/HSU - ideal for battery-powered mobile accessories. |
Applications
| Mobile Payment Terminal | Secure Access Badge |
|---|---|
Use Scenario: Contactless EMV payment initiation via smartphone or POS terminal using MIFARE Classic 4K cards. IC Role / Device Role / Timing Role: PN5321A3HN/C106518 acts as ISO/IEC 14443A Reader/Writer with MIFARE encryption acceleration and 424 kbit/s throughput. Use Value: Enables sub-300 ms transaction time with full cryptographic handshake, meeting PCI PTS v6.0 timing requirements for tap-to-pay. |
Use Scenario: Employee badge emulation in corporate door readers compliant with HID iCLASS or MIFARE DESFire EV2. IC Role / Device Role / Timing Role: PN5321A3HN/C106518 operates in ISO/IEC 14443A card emulation mode with load modulation via LOADMOD pin. Use Value: Achieves 100 mm operational distance (vs. 50 mm in Reader mode), allowing hands-free authentication at standard doorway standoff. |
| NFC Peer-to-Peer Data Exchange | Industrial Asset Tagging |
Use Scenario: Two-way contactless file sharing between smartphones or tablets using NFCIP-1 Active/Passive modes. IC Role / Device Role / Timing Role: PN5321A3HN/C106518 functions as both Initiator and Target with full NFCIP-1 framing and error detection at 424 kbit/s. Use Value: Supports SNEP (Simple NDEF Exchange Protocol) with deterministic latency under 15 ms per 128-byte NDEF record. |
Use Scenario: Ruggedized equipment ID tag scanned by handheld reader in factory floor environments. IC Role / Device Role / Timing Role: PN5321A3HN/C106518 serves as FeliCa Reader/Writer interfacing with legacy Japanese transit-style tags. Use Value: Delivers 50 mm read range despite metal-mount constraints due to integrated RF level detector and adaptive tuning registers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7150B0HN/C1 | Smaller HVQFN32 package; integrated firmware; no 80C51 user-accessible core; lower max data rate (106 kbit/s only). | Targeted at cost-sensitive consumer electronics requiring fixed-function NFC; lacks MIFARE Classic 4K or FeliCa support. | Select when design prioritizes footprint reduction and simplified certification over protocol flexibility. |
| ST25DV04KC | I²C-only interface; EEPROM-based dynamic NDEF storage; no microcontroller; no Reader/Writer capability - pure NFC tag IC. | Used exclusively for passive tag emulation (e.g., smart posters, product labels); cannot initiate communication or run custom firmware. | Select only for static NFC tag applications; not a functional substitute for PN5321A3HN/C106518's dual-mode controller role. |
Compared with PN7150B0HN/C1 and ST25DV04KC, PN5321A3HN/C106518 uniquely combines full 80C51 programmability, six protocol modes (including FeliCa and NFCIP-1), and hardware-accelerated crypto - making it the only option for field-upgradable, multi-standard NFC gateways in industrial and payment-grade designs.
Availability
PN5321A3HN/C106518 is available at Aetrix Electronics and suitable for mobile payment terminals, secure access systems, NFC peer-to-peer data exchange, and industrial asset tagging requiring stable component supply across long-lifecycle deployments.
Supply support for PN5321A3HN/C106518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and mobile markets, with deep expertise in RFID, NFC, and trusted execution environments.
PN5321A3HN/C106518 belongs to NXP's PN53x NFC controller family, designed specifically for high-reliability, multi-protocol contactless communication in battery-powered and security-critical embedded systems.
FAQ
What communication protocols does the PN5321A3HN/C106518 support?
The PN5321A3HN/C106518 supports six distinct contactless protocols: ISO/IEC 14443A/MIFARE Reader/Writer and Card Emulation, FeliCa Reader/Writer and Card Emulation, ISO/IEC 14443B Reader/Writer, and ISO/IEC 18092 NFCIP-1 Peer-to-Peer (both Active and Passive modes). It handles full framing, CRC-16, and parity for all supported standards, with maximum data rates up to 424 kbit/s in each direction.
Does the PN5321A3HN/C106518 require external components for antenna connection?
No, the PN5321A3HN/C106518 features buffered output drivers and integrated matching circuitry that allow direct connection to a printed PCB antenna without additional active components. Only passive LC tuning elements (capacitors/inductors) are needed to resonate at 13.56 MHz, and the integrated RF level detector enables automatic field detection for NFCIP-1 initiator activation.
How does the PN5321A3HN/C106518 achieve secure card functionality?
The PN5321A3HN/C106518 itself does not provide secure storage but enables secure card functionality through the NFC-WI/S2C interface, which connects to an external secure IC (e.g., NXP A700x or Infineon SLB9670). Its dedicated SVDD power switch supplies the secure IC, and the interface supports encrypted data exchange - ensuring keys and credentials remain isolated from the main controller firmware.
What are the power consumption characteristics of the PN5321A3HN/C106518 in low-power modes?
The PN5321A3HN/C106518 offers two ultra-low-power states: Hard-Power-Down mode draws just 1 µA typical (VBAT = 5 V), fully disabling all circuits except RSTPD_N monitoring; Soft-Power-Down consumes 22 µA typical with RF level detector active, enabling automatic wake-up on host interface activity (SPI/I²C/HSU) or external field detection - critical for battery-operated NFC readers.
Can the PN5321A3HN/C106518 operate at data rates higher than 424 kbit/s?
Yes - while the integrated analog front-end supports up to 424 kbit/s, the PN5321A3HN/C106518's digital CIU block can process data at up to 3.39 Mbit/s. To achieve this, external analog components must be connected to the SIGIN/SIGOUT pins to handle modulation/demodulation, as specified in the datasheet's "Higher Transfer Speeds" section. This extension requires custom RF design and firmware adaptation.
PN5321A3HN/C106518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- RFID Reader/Transponder
- Frequency:
- 13.56MHz
- Standards:
- FeliCa, ISO 14443A, ISO 14443B, ISO 18092, Mifare, NFC
- Interface:
- I2C, SPI, UART
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -30°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-HVQFN (6x6)
PN5321A3HN/C106518 FAQ
1.How can I place an order for PN5321A3HN/C106518 through Aetrix?
Please submit a Request for Quotation (RFQ) for PN5321A3HN/C106518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN5321A3HN/C106518 reliable?
The price and inventory of PN5321A3HN/C106518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN5321A3HN/C106518 is usually 5 days.
3.What payment methods are accepted for PN5321A3HN/C106518?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN5321A3HN/C106518 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN5321A3HN/C106518?
PN5321A3HN/C106518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN5321A3HN/C106518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN5321A3HN/C106518?
For technical support, including PN5321A3HN/C106518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN5321A3HN/C106518 requirements.
6.How does Aetrix verify that PN5321A3HN/C106518 is sourced from the original manufacturer or authorized distributors?
All PN5321A3HN/C106518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN5321A3HN/C106518 meets industry standards.
7.What is the process for return or replacement of PN5321A3HN/C106518?
All PN5321A3HN/C106518 units undergo pre-shipment inspection (PSI). If there is an issue with PN5321A3HN/C106518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN5321A3HN/C106518 part is unused and in its original packaging.
Return procedure for PN5321A3HN/C106518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PN5321A3HN/C106518 Tags

-
SL2S2602FTBX
NXP Semiconductors

-
ST25DV04K-IER6S3
STMicroelectronics

-
ST25DV04K-IER6C3
STMicroelectronics

-
LXMSJZNCMD-217
Murata Electronics

-
NT3H2111W0FTTJ
NXP Semiconductors

-
NT3H2111W0FHKH
NXP Semiconductors

-
M24LR04E-RMC6T/2
STMicroelectronics

-
ST25DV04KC-JF6D3
STMicroelectronics

-
ST25DV64KC-IE6S3
STMicroelectronics
-
ST25DV64K-IER6T3
STMicroelectronics

-
NT3H2211W0FTTJ
NXP Semiconductors

-
NT3H2211W0FHKH
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

