NXP Semiconductors PN7160A1HN/C100E
- Part No.:
- PN7160A1HN/C100E
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
PN7160A1HN/C100E.pdf
- Description:
- IC NFC CONTROLLER I2C HVQFN40
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PN7160A1HN/C100E from NXP Semiconductors is a Near Field Communication (NFC) controller IC with integrated NCI 2.0 interface, firmware version 12.50.05, and I²C host interface - designed for card emulation, reader/writer, and peer-to-peer modes in mobile and portable devices. It supports ISO/IEC 14443 A/B, ISO/IEC 15693, MIFARE, FeliCa, and NFC Forum Tags T1–T5, with 1.3 W transmitter output power and 20 mVp-p card-mode receiver sensitivity.
For engineers reviewing the PN7160A1HN/C100E datasheet, PN7160A1HN/C100E pinout, PN7160A1HN/C100E application, or PN7160A1HN/C100E equivalent, key selection considerations include its HVQFN40 package, autonomous low-power polling loop (100 µA typical), integrated power management for 2.8–5.5 V battery supply, and support for NFC Forum-certified T4T card emulation with NDEF write capability from RF side.
Technical Context
The PN7160A1HN/C100E implements an ARM Cortex-M0 core with 128 kB ROM, 28 kB EEPROM, and 8 kB SRAM, executing NXP's certified firmware stack compliant with NFC Forum Device Requirements and NCI 2.0. Its RF front-end features enhanced dynamic load modulation amplitude (DLMA), independent 5° LMA phase adjustment per Type A/B/F, and dynamic power control to maximize field strength without exceeding regulatory limits.
It operates across three system power modes - Full Power, Autonomous (host-off card emulation), and Low-Power (VBAT-only) - with wake-up via RF field, internal timer, or host interface. The device integrates a 27.12 MHz crystal oscillator, fractional-N PLL, and dual-LDO power architecture supporting direct battery connection and external DC-DC enable (PCA941xA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Battery Supply Range | 2.8 V to 5.5 V - enables direct integration into single-cell Li-ion or multi-cell battery systems without external regulators. |
| Transmitter Output Power | 1.3 W - delivers extended read range in PCD mode while complying with ISO/IEC 14443 power limits at 0 mm distance. |
| Card Mode Sensitivity | 20 mVp-p - ensures reliable PICC detection under weak field conditions, critical for small-form-factor antennas. |
| Low-Power Polling Current | 100 µA @ 500 ms loop - sustains background tag discovery during host sleep without compromising system battery life. |
| Firmware Version | 12.50.05 - production firmware with NFC Forum certification for reader, card, and P2P modes (up to FW 12.50.0A). |
| Host Interface | I²C-bus High-Speed mode - simplifies host integration with standard two-wire protocol and minimal GPIO overhead. |
| Operating Temperature | −30 °C to +85 °C - qualified for industrial and consumer portable equipment environments. |
Pinout & Package
HVQFN40 package (SOT618-1), 40-terminal thermal-enhanced quad flat no-lead, 6 × 6 mm body, 0.5 mm pitch, exposed thermal pad (VSS center).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (I2C_ADR0/SPI_NSS) | I²C address select / SPI slave select | Configures I²C device address (0x28 or 0x29); enables SPI communication when asserted low. |
| 8 (IRQ) | Interrupt request output | Active-low signal alerts host of RF events (e.g., tag detection, command completion) without polling. |
| 10 (VEN) | Hard Power Down enable input | Drives device into minimum-power HPD state when pulled low; retains AutoMode bit across reset. |
| 15–16 (RXN/RXP) | Differential receiver inputs | Accepts analog RF signals from antenna matching network; enables high-sensitivity card-mode operation. |
| 19–21 (TX2/TX1) | RF transmitter outputs | Drive tuned antenna circuit; support up to 1.3 W output with VDD(TX) = 5.25 V and 250 mA antenna current limit. |
| 23–24 (ANT1/ANT2) | Antenna wake-up sense inputs | Enable RF-field-triggered wake-up from Standby without host intervention or VDD(PAD) supply. |
| 37 (DCDC_EN) | External DC-DC enable request | Signals external PCA941xA DC-DC converter to boost TX supply voltage for higher output power. |
| 39 (WKUP_REQ) | Wake-up request input | Allows host to initiate transition from Standby to Active state on demand, synchronizing with system activity. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Polling Loop | Autonomous 500 ms low-power discovery cycle reduces host CPU load and extends battery life in always-on NFC applications. |
| Enhanced DLMA | Real-time load modulation amplitude optimization improves communication range in card emulation mode under varying field strengths. |
| Dynamic Power Control | Adjusts transmitter output in real time to maintain maximum legal field strength at contact (0 mm), improving reliability with diverse tags. |
| Autonomous Card Emulation | Delivers NDEF short records in T4T mode with host powered off - essential for secure element-less payment and access credential use cases. |
| Anti-Tearing EEPROM | Hardware-supported recovery from power loss during EEPROM writes prevents corruption of stored credentials or configuration data. |
Applications
| Mobile Payment Terminals | Wearable Health Monitors |
|---|---|
|
Use Scenario: Contactless payment initiation via tap-to-pay on compact handheld terminals with limited PCB area and battery capacity. IC Role / Device Role / Timing Role: NFC controller handling secure card emulation (T4T), reader mode for QR code pairing, and P2P for device provisioning. Use Value: 100 µA low-power polling enables >7-day standby with daily transaction usage; HVQFN40 footprint minimizes layout space vs. legacy solutions. |
Use Scenario: Tap-based health data exchange between wearable and smartphone, including encrypted biometric logs and firmware updates. IC Role / Device Role / Timing Role: Acts as NFC initiator (reader) to read smartphone NDEF records and target (card) to expose device identity and status. Use Value: Integrated 28 kB EEPROM stores cryptographic keys and sensor calibration data; autonomous wake-up via ANT1/ANT2 eliminates host polling latency. |
| Smart Home Gateways | Industrial Asset Tag Readers |
|
Use Scenario: NFC-enabled home hub authenticating smart locks, thermostats, and lighting controllers during setup and firmware update. IC Role / Device Role / Timing Role: Reader/writer for MIFARE DESFire and ISO/IEC 14443B credentials; supports embedded T4T for device onboarding. Use Value: 1.3 W transmitter output ensures reliable read of passive tags through plastic enclosures; 2.8–5.5 V supply range matches common 3.3 V or 5 V gateway rails. |
Use Scenario: Ruggedized handheld reader scanning ISO/IEC 15693 asset tags in factory environments with temperature extremes and EMI noise. IC Role / Device Role / Timing Role: High-sensitivity PICC mode receiver (20 mVp-p) coupled with PRBS support for robust ICODE VCD interrogation. Use Value: −30 °C to +85 °C operation meets industrial ambient requirements; integrated RF level detector enables adaptive gain control in noisy settings. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7160A1EV/C100E | VFBGA64 package (64-ball), smaller footprint but requires microvia routing; same firmware and I²C interface. | Better suited for space-constrained mobile designs where board area is more critical than assembly cost. | Select when PCB real estate is premium and fine-pitch assembly capability exists. |
| PN7161A1HN/C100E | Includes Apple Enhanced Contactless Polling (ECP) support; model ID 0x71; otherwise identical pinout and firmware baseline. | Required for iOS accessory certification and EMVCo-compliant contactless payment readers targeting Apple ecosystem. | Choose only if formal ECP authorization is obtained and Apple interoperability is mandatory. |
Compared with PN7160A1HN/C100E, the VFBGA64 variant offers denser integration but higher assembly complexity, while the PN7161A1HN/C100E adds ECP capability at identical cost and form factor - making it the sole upgrade path for Apple-authorized deployments.
Availability
PN7160A1HN/C100E is available at Aetrix Electronics and suitable for mobile payment terminals, wearable health monitors, smart home gateways, and industrial asset tag readers requiring stable component supply and long-term lifecycle support.
Supply support for PN7160A1HN/C100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer markets, with over 20 years of NFC innovation.
The PN7160 series belongs to NXP's NFC Controller product line, engineered to simplify NFC integration in battery-powered portable devices by minimizing external components, optimizing power efficiency, and delivering certified interoperability across NFC Forum, EMVCo, and ISO standards.
FAQ
What host interfaces does the PN7160A1HN/C100E support?
The PN7160A1HN/C100E supports I²C-bus High-Speed mode as its primary host interface, configured via pins I2C_ADR0/I2C_ADR1 for address selection and I2C_SDA/I2C_SCL for data/clock. It also implements the NFC Forum NCI 2.0 logical interface over I²C, enabling standardized command/response messaging. SPI is not supported on this specific variant (denoted by "A" in part number), unlike PN7160B1HN/C100E.
Does the PN7160A1HN/C100E support card emulation without host processor involvement?
Yes, the PN7160A1HN/C100E supports Autonomous Card Emulation mode. When configured by the host and placed in Standby or Low-Power mode, it can independently present an NDEF short record in T4T format using its embedded 28 kB EEPROM - even when the host processor is fully powered down. This functionality relies on firmware version 12.50.05 and requires proper antenna tuning and IRQ/WKUP_REQ pin configuration.
What is the significance of the "HN" and "C100E" suffixes in PN7160A1HN/C100E?
"HN" indicates the HVQFN40 package (SOT618-1), a 6 × 6 mm thermal-enhanced quad flat no-lead variant with 40 terminals and exposed thermal pad. "C100E" specifies firmware version 12.50.05, I²C interface ("A"), and 1-tray packing (490 units). The "1" denotes first revision; "E" in C100E is the packing code, not a temperature grade or reliability variant.
Can the PN7160A1HN/C100E drive large antennas requiring >250 mA transmitter current?
No - the PN7160A1HN/C100E's transmitter is rated for continuous antenna current up to 250 mA, as defined in its quick reference data. Exceeding this risks thermal shutdown or non-compliance with ISO/IEC 14443 power limits. For higher output, NXP recommends pairing with external DC-DC converters like PCA941xA (enabled via DCDC_EN pin), which can extend VDD(TX) beyond 5.25 V while maintaining safe current levels in the IC itself.
Is the PN7160A1HN/C100E compatible with Apple's Enhanced Contactless Polling (ECP)?
No - PN7160A1HN/C100E is based on the PN7160 family and does not support Apple ECP. Only PN7161 variants (e.g., PN7161A1HN/C100E) include ECP functionality, identifiable by model ID 0x71 in the CORE_RESET_NTF response. ECP support requires formal Apple authorization and is not enabled by default, even on PN7161 devices.
PN7160A1HN/C100E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Standards:
- FeliCa, ISO 14443, ISO 15693, MIFARE, NFC
- Interface:
- I2C
- Voltage - Supply:
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Operating Temperature:
- -25°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-HVQFN (6x6)
PN7160A1HN/C100E FAQ
1.How can I place an order for PN7160A1HN/C100E through Aetrix?
Please submit a Request for Quotation (RFQ) for PN7160A1HN/C100E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN7160A1HN/C100E reliable?
The price and inventory of PN7160A1HN/C100E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN7160A1HN/C100E is usually 5 days.
3.What payment methods are accepted for PN7160A1HN/C100E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN7160A1HN/C100E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN7160A1HN/C100E?
PN7160A1HN/C100E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN7160A1HN/C100E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN7160A1HN/C100E?
For technical support, including PN7160A1HN/C100E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN7160A1HN/C100E requirements.
6.How does Aetrix verify that PN7160A1HN/C100E is sourced from the original manufacturer or authorized distributors?
All PN7160A1HN/C100E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN7160A1HN/C100E meets industry standards.
7.What is the process for return or replacement of PN7160A1HN/C100E?
All PN7160A1HN/C100E units undergo pre-shipment inspection (PSI). If there is an issue with PN7160A1HN/C100E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN7160A1HN/C100E part is unused and in its original packaging.
Return procedure for PN7160A1HN/C100E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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