NXP Semiconductors PN7160B1HN/C100Y
- Part No.:
- PN7160B1HN/C100Y
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
PN7160B1HN/C100Y.pdf
- Description:
- IC NFC CONTROLLER SPI HVQFN40
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PN7160B1HN/C100Y from NXP Semiconductors is a SPI-interface NFC controller with integrated NCI 2.0 firmware, supporting ISO/IEC 14443A/B, ISO/IEC 15693, MIFARE, FeliCa, and NFC Forum T4T/T5T protocols. It delivers 1.3 W transmitter output power, 20 mV(p-p) card-mode receiver sensitivity, and operates across 2.8–5.5 V battery supply. Designed for mobile and portable devices requiring autonomous card emulation during host shutdown.
For engineers reviewing the PN7160B1HN/C100Y datasheet, PN7160B1HN/C100Y pinout, PN7160B1HN/C100Y application, or PN7160B1HN/C100Y equivalent, key selection criteria include SPI host interface compatibility, HVQFN40 package footprint, low-power polling loop current (100 μA typ.), integrated RF front-end performance, and support for NFC Forum-certified reader/card/P2P modes up to firmware v12.50.0A.
Technical Context
The PN7160B1HN/C100Y implements an ARM Cortex-M0 core with 128 kB ROM, 28 kB EEPROM, and 8 kB SRAM, executing NCI 2.0-compliant firmware. Its RF architecture features enhanced dynamic load modulation amplitude (DLMA), independent 5° LMA phase adjustment per Type A/B/F, and dynamic power control compliant with NFC standards at zero distance.
It supports three system power modes-Full Power, Autonomous (host-off card emulation), and Low-Power-with wake-up via RF field, internal timer, or host interfaces. The integrated power management unit accepts direct battery input (2.8–5.5 V), includes TXLDO and DSLDO regulators, and enables hard power-down via VEN pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Battery Supply Range | 2.8 V to 5.5 V - Enables direct connection to Li-ion/Li-poly batteries without external regulation. |
| Transmitter Output Power | 1.3 W - Supports extended read range and robust communication with passive tags in noisy environments. |
| Card Mode Sensitivity | 20 mV(p-p) - Ensures reliable detection of weak RF fields from legacy or low-power cards. |
| Low-Power Polling Current | 100 μA typ. at 500 ms loop - Minimizes standby power in always-on NFC applications like smart locks or wearables. |
| Firmware Version | v12.50.05 - Production baseline supporting NFC Forum certification for reader/card/P2P modes (up to v12.50.0A). |
| Host Interface | SPI-bus - Provides deterministic timing and higher throughput than I²C for high-frequency tag polling. |
| Operating Temperature | −30 °C to +85 °C - Qualified for industrial and automotive-adjacent portable electronics deployment. |
Pinout & Package
HVQFN40 package (SOT618-1), 6 × 6 mm, 0.5 mm pitch, exposed thermal pad. Compatible with standard reflow profiles and space-constrained PCB layouts in mobile and wearable designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: I2C_ADR0/SPI_NSS | Host interface select / chip enable | SPI slave select input; asserted low to enable SPI communication with PN7160B1HN/C100Y. |
| 5: I2C_SDA/SPI_MISO | Host data output | SPI master input / slave output; carries NCI responses and status notifications from PN7160B1HN/C100Y. |
| 7: I2C_SCL/SPI_SCK | Clock input | SPI clock input; synchronizes data transfer between host and PN7160B1HN/C100Y at up to High-Speed mode rates. |
| 8: IRQ | Interrupt request output | Open-drain active-low signal indicating event completion (e.g., tag detected, command processed) to host processor. |
| 10: VEN | Hard power-down control | Active-low enable; drives PN7160B1HN/C100Y into <16 μA HPD state when pulled below 0.4 V. |
| 14: VDD(TX) | Transmitter supply | Input for 2.7–5.25 V dedicated TX rail; decoupled locally to sustain 1.3 W RF output without droop. |
| 21: TX1 & 19: TX2 | Differential antenna drivers | Complementary outputs driving tuned antenna matching network; support balanced or single-ended configurations. |
| 15/16: RXN/RXP | Differential receiver inputs | High-sensitivity analog front-end inputs; accept 20 mV(p-p) signals for card emulation detection. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated RF front-end with DLMA | Enables >20% extended communication range in card mode by dynamically optimizing load modulation amplitude per field strength. |
| Autonomous card emulation | Permits NDEF message presentation without host CPU power-critical for secure element handoff and battery-critical wearables. |
| Flexible clock supply | Supports 27.12 MHz crystal via NFC_CLK_XTAL1 or external clock; PLL allows host clock reuse to reduce BOM count. |
| Integrated polling loop | Hardware-accelerated discovery sequence reduces host firmware overhead and ensures consistent 500 ms polling intervals. |
| Anti-tearing EEPROM | Guarantees atomic NDEF record updates during unexpected power loss-essential for payment and credential storage. |
| NFC Forum T4T compliance | Validated interoperability with Android TagWriter and other T4T-compliant readers for reliable NDEF short record exchange. |
Applications
| Smartphone NFC Subsystem | Wearable Access Control |
|---|---|
|
Use Scenario: Embedded in mid-tier smartphones to provide contactless payment, transit ticketing, and peer-to-peer file sharing. IC Role / Device Role / Timing Role: Primary NFC controller interfacing with secure element and application processor via SPI and NCI 2.0. Use Value: Reduces PCB area by 35% vs discrete NFC solutions and enables sub-100 μA standby current for all-day always-on functionality. |
Use Scenario: Integrated into fitness trackers and smartwatches for tap-to-unlock doors, hotel room access, and loyalty card emulation. IC Role / Device Role / Timing Role: Standalone card emulator operating autonomously during host sleep; wakes host only on valid tag interaction. Use Value: Extends battery life by eliminating continuous host polling while maintaining instant response to NFC field presence. |
| Smart Home Gateway Hub | Industrial Asset Tag Reader |
|
Use Scenario: Used in Wi-Fi/Zigbee gateways to provision IoT sensors, configure mesh nodes, and authenticate peripherals via NFC. IC Role / Device Role / Timing Role: Reader/writer controller managing multiple tag types (MIFARE, ISO15693, T4T) with firmware-updatable protocol stack. Use Value: Eliminates need for external level shifters or voltage translators-supports 3.3 V host I/O and 5.5 V battery directly. |
Use Scenario: Deployed in handheld maintenance tools for reading maintenance logs, calibration data, and firmware versions from industrial equipment tags. IC Role / Device Role / Timing Role: High-reliability PCD-mode reader with dynamic power control ensuring compliance with ISO14443 limits at 0 cm distance. Use Value: Delivers 1.3 W output to read damaged or poorly coupled tags in metal-rich environments where standard readers fail. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7160A1HN/C100Y | I²C interface instead of SPI; identical firmware (v12.50.05), HVQFN40 package, same RF specs. | Preferred where host SoC has limited SPI peripherals but robust I²C infrastructure and lower pin-count constraints. | Select PN7160A1HN/C100Y if host design uses I²C for other peripherals and requires simplified signal routing. |
| PN7161B1HN/C100Y | Adds Apple Enhanced Contactless Polling (ECP); requires formal authorization; otherwise identical pinout, SPI interface, and HVQFN40 package. | Required for iOS device pairing and certified ECP-enabled accessories; not usable without NXP ECP license. | Choose PN7161B1HN/C100Y only when developing for Apple ecosystem integration and ECP authorization is secured. |
Compared with PN7160A1HN/C100Y, PN7160B1HN/C100Y offers deterministic SPI timing for high-throughput polling, while PN7161B1HN/C100Y adds proprietary ECP capability at the cost of licensing dependency-neither is pin-compatible with non-HN variants due to package-specific ball/lead mapping.
Availability
PN7160B1HN/C100Y is available at Aetrix Electronics and suitable for smartphone subsystems, wearable access control, smart home gateways, and industrial asset tag readers requiring stable component supply and long-term lifecycle support.
Supply support for PN7160B1HN/C100Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and mobile markets, with over 20 years of NFC innovation.
The PN7160 product line targets compact, low-power NFC integration in battery-operated consumer and industrial devices-designed to minimize external components, simplify antenna tuning, and enable host-off operation for energy-sensitive applications.
FAQ
What host interface does PN7160B1HN/C100Y support?
PN7160B1HN/C100Y supports SPI-bus host interface exclusively, as indicated by the "B" in its part number suffix. It implements NCI 2.0 protocol over SPI, enabling full reader, card emulation, and P2P functionality. Unlike I²C variants (e.g., PN7160A1HN/C100Y), it does not support I²C communication-SPI must be used for all command/response exchanges with the host processor.
Does PN7160B1HN/C100Y support Apple Enhanced Contactless Polling (ECP)?
No, PN7160B1HN/C100Y does not support ECP. Only PN7161-series parts (e.g., PN7161B1HN/C100Y) include ECP functionality, and even then, it requires formal authorization from NXP. PN7160B1HN/C100Y is functionally identical to PN7160A1HN/C100Y except for its SPI interface-it lacks ECP hardware enablement and associated firmware features.
What is the minimum current consumption of PN7160B1HN/C100Y in low-power polling mode?
PN7160B1HN/C100Y consumes 100 μA typical in low-power polling loop mode at VBAT = 3.6 V and 500 ms loop time, as specified in Table 1 of the datasheet. This value assumes use of the enhanced RF detector and reflects active RF sensing with CPU and most peripherals powered down-enabling multi-week battery life in always-on wearable applications.
Can PN7160B1HN/C100Y operate without a host processor powered on?
Yes, PN7160B1HN/C100Y supports Autonomous mode: when configured by the host and placed in standby, it can independently perform card emulation (e.g., present NDEF records) using its internal EEPROM and RF front-end-even with VDD(PAD) off and host CPU in deep sleep. Wake-up occurs only upon valid RF field detection or timer expiry, minimizing system-level power draw.
What package type and dimensions does PN7160B1HN/C100Y use?
PN7160B1HN/C100Y uses the HVQFN40 package (SOT618-1): a 6 mm × 6 mm, 0.5 mm pitch, thermally enhanced quad flat no-lead package with 40 terminals and an exposed center pad. This package supports automated assembly, efficient heat dissipation during 1.3 W RF transmission, and compact layout in space-constrained mobile and wearable PCBs.
PN7160B1HN/C100Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Standards:
- FeliCa, ISO 14443, ISO 15693, MIFARE, NFC
- Interface:
- SPI
- Voltage - Supply:
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Operating Temperature:
- -25°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-HVQFN (6x6)
PN7160B1HN/C100Y FAQ
1.How can I place an order for PN7160B1HN/C100Y through Aetrix?
Please submit a Request for Quotation (RFQ) for PN7160B1HN/C100Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN7160B1HN/C100Y reliable?
The price and inventory of PN7160B1HN/C100Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN7160B1HN/C100Y is usually 5 days.
3.What payment methods are accepted for PN7160B1HN/C100Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN7160B1HN/C100Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN7160B1HN/C100Y?
PN7160B1HN/C100Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN7160B1HN/C100Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN7160B1HN/C100Y?
For technical support, including PN7160B1HN/C100Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN7160B1HN/C100Y requirements.
6.How does Aetrix verify that PN7160B1HN/C100Y is sourced from the original manufacturer or authorized distributors?
All PN7160B1HN/C100Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN7160B1HN/C100Y meets industry standards.
7.What is the process for return or replacement of PN7160B1HN/C100Y?
All PN7160B1HN/C100Y units undergo pre-shipment inspection (PSI). If there is an issue with PN7160B1HN/C100Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN7160B1HN/C100Y part is unused and in its original packaging.
Return procedure for PN7160B1HN/C100Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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