NXP Semiconductors PN7161B1HN/C100E
- Part No.:
- PN7161B1HN/C100E
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
PN7161B1HN/C100E.pdf
- Description:
- IC NFC CONTROLLER SPI HVQFN40
- Quantity:
- Payment:

- Shipping:

Inventory:187
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Product details
Overview
PN7161B1HN/C100E from NXP Semiconductors is a SPI-interface NFC controller with integrated firmware, supporting ISO/IEC 14443A/B, FeliCa, MIFARE, and NFC Forum T4T/T5T protocols. It delivers 1.3 W transmitter output power, achieves 20 mV(p-p) card-mode receiver sensitivity, and operates across 2.8–5.5 V battery supply. It enables autonomous card emulation during host shutdown in mobile and wearable devices.
For engineers reviewing the PN7161B1HN/C100E datasheet, PN7161B1HN/C100E pinout, PN7161B1HN/C100E application, or PN7161B1HN/C100E equivalent, key selection criteria include ECP support (PN7161-specific), HVQFN40 package compatibility, NCI 2.0 interface compliance, low-power polling loop current (100 µA typ.), and firmware version 12.50.05 preloaded at shipment.
Technical Context
The PN7161B1HN/C100E implements an NCI 2.0-compliant host interface over SPI, with integrated ARM Cortex-M0 coprocessor, 8 kB SRAM, 128 kB ROM, and 28 kB EEPROM for firmware and configuration storage. Its RF front-end supports active load modulation and Enhanced Dynamic LMA for extended range in card mode.
It features dual power domains: VBAT (2.8–5.5 V) powers the RF transmitter and core logic, while VDD(PAD) (3.0–3.6 V) supplies the SPI interface. Power states include Hard Power Down (10.5 µA), Standby (32–52 µA), and low-power polling loop (100 µA), all configurable via firmware without host intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Battery supply range | 2.8 V to 5.5 V - enables direct connection to Li-ion/Li-poly battery rails without external regulators |
| Transmitter output power | 1.3 W - supports robust reader mode operation with large antenna designs or metal-adjacent placement |
| Card-mode sensitivity | 20 mV(p-p) - ensures reliable detection of weak-field cards (e.g., thin wallets, embedded tags) |
| Low-power polling current | 100 µA (typ.) at 500 ms loop - extends battery life in always-on NFC wake-up applications |
| Firmware version | 12.50.05 - production baseline supporting ECP (Apple), EMVCo profile, and T4T NDEF write from RF |
| Host interface | SPI-bus (High-speed mode) - provides deterministic timing and reduced pin count vs. I²C in space-constrained layouts |
| Operating temperature | −30 °C to +85 °C - qualified for industrial-grade portable and automotive-accessory environments |
Pinout & Package
HVQFN40 (SOT618-1) package: 40-terminal, thermally enhanced, leadless quad flat package with exposed thermal pad (VSS center pad). Pitch: 0.4 mm. Dimensions: 5.0 × 5.0 × 0.85 mm. RoHS-compliant, halogen-free, matte tin finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (I2C_ADR0/SPI_NSS) | SPI slave select / chip enable | Active-low signal asserting SPI transaction start; pulled high internally when unused |
| 5 (I2C_SDA/SPI_MISO) | SPI master-in-slave-out data line | Bi-directional data path for firmware download and NCI command/response exchange |
| 7 (I2C_SCL/SPI_SCK) | SPI clock input | Accepts up to 10 MHz clock; synchronous timing critical for NCI frame integrity |
| 8 (IRQ) | Interrupt request output | Open-drain, active-low signal notifying host of RF event, firmware update completion, or error condition |
| 10 (VEN) | Hard Power Down enable | Drives device into <16 µA HPD state when held low; reset source independent of VBAT |
| 14 (VDD(TX)) | Transmitter supply voltage | 2.7–5.25 V input powering RF output stage; decoupling required per layout guidelines |
| 21 & 19 (TX1, TX2) | Differential antenna driver outputs | Drive balanced antenna matching network; support 50 Ω differential or single-ended configurations |
| 15 & 16 (RXN, RXP) | Differential receiver inputs | Accept 20 mV(p-p) minimum signal; require matched trace routing and 50 Ω termination |
| 23 & 24 (ANT1, ANT2) | Wake-up antenna sense inputs | Enable RF-field-triggered wake from Standby without host involvement; internal biasing applied |
| 37 (DCDC_EN) | External DC-DC enable request | Signals external PCA941xA regulator to boost VDD(TX); synchronizes with transmit burst timing |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced Contactless Polling (ECP) | Enables Apple-certified fast tag discovery and dynamic polling optimization - exclusive to PN7161 family |
| Autonomous Card Emulation | Permits NDEF message presentation in T4T mode with host powered off - no VDD(PAD) required |
| Integrated RF level detector | Eliminates need for external RSSI circuitry; enables adaptive polling interval adjustment based on field strength |
| Dynamic Power Control (DPC) | Maintains maximum legal output power (EMVCo/NFC Forum) across varying antenna coupling conditions |
| Anti-tearing support | Hardware-protected EEPROM writes prevent corruption during unexpected power loss during firmware updates |
| Flexible clock architecture | Supports 27.12 MHz crystal (NFC_CLK_XTAL1/XTAL2) or external clock input - simplifies BOM and layout |
Applications
| Smartphone NFC Module | Wearable Payment Terminal |
|---|---|
|
Use Scenario: Integration into flagship smartphone mainboard for contactless payment, transit ticketing, and peer-to-peer sharing. IC Role / Device Role / Timing Role: Primary NFC controller handling all RF protocol stacks (T4T, MIFARE, FeliCa) and NCI 2.0 host communication. Use Value: 1.3 W output power enables reliable read/write at >4 cm distance; autonomous card emulation allows secure element handoff without AP wake-up. |
Use Scenario: Embedded in wristband or smart ring for tap-to-pay in offline mode with local token storage. IC Role / Device Role / Timing Role: Standalone NFC interface managing secure NDEF exchange with POS terminals while host MCU sleeps. Use Value: 100 µA low-power polling loop extends battery life to >14 days; ECP support reduces transaction latency by 30% in crowded RF environments. |
| Smart Home Gateway | Industrial Asset Tag Reader |
|
Use Scenario: NFC-enabled home hub authenticating smart locks, lighting, and HVAC controllers via T5T NDEF records. IC Role / Device Role / Timing Role: Reader/writer controller interfacing with multiple ISO/IEC 15693 tags using PRBS-modulated commands. Use Value: Dual antenna inputs (ANT1/ANT2) allow simultaneous wake-up detection and active polling - eliminates missed tag events during sleep cycles. |
Use Scenario: Handheld maintenance tool reading encrypted MIFARE DESFire EV2 tags on factory equipment. IC Role / Device Role / Timing Role: High-reliability PCD controller executing EMVCo-compliant transactions in noisy industrial EMI environments. Use Value: 20 mV(p-p) sensitivity ensures read success even with corroded or shielded tags; DPC maintains consistent field strength across battery discharge curve. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7160B1HN/C100E | Lacks ECP support; identical pinout, firmware baseline 12.50.05, same HVQFN40 package and SPI interface | Not suitable for Apple ecosystem integration or EMVCo-certified fast polling; otherwise functionally interchangeable | Select when ECP is not required and cost optimization is prioritized over future-proofing |
| PN7161B1HN/C101E | Same package and interface; ships with firmware v12.50.11 featuring improved ECP stability and XTAL startup robustness | Required for new designs targeting latest Apple ECP certification or resolving known crystal startup issues in cold environments | Choose for production releases requiring validated ECP behavior under dynamic field conditions |
Compared with PN7160B1HN/C100E, PN7161B1HN/C100E adds ECP capability essential for iOS pairing and faster tag discovery, while PN7161B1HN/C101E further enhances reliability in marginal crystal-start scenarios - making it the recommended choice for volume production targeting global NFC interoperability.
Availability
PN7161B1HN/C100E is available at Aetrix Electronics and suitable for smartphone NFC modules, wearable payment terminals, smart home gateways, and industrial asset tag readers requiring stable component supply and long-term lifecycle support.
Supply support for PN7161B1HN/C100E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer markets, with headquarters in Eindhoven, Netherlands.
The PN7161 belongs to NXP's PN7160/PN7161 NFC controller product line, designed specifically for ultra-low-power, high-performance NFC integration in battery-powered mobile and IoT endpoints where ECP compliance and autonomous operation are critical.
FAQ
What distinguishes PN7161B1HN/C100E from PN7160B1HN/C100E?
The PN7161B1HN/C100E integrates Enhanced Contactless Polling (ECP) support - a feature authorized by Apple for optimized tag discovery and iOS pairing - which is absent in PN7160B1HN/C100E. Both share identical HVQFN40 packaging, SPI interface, firmware version 12.50.05, and electrical specifications. The PN7161B1HN/C100E also supports ECP in EMVCo profiles, enabling faster transaction initiation in certified payment terminals.
Does PN7161B1HN/C100E support autonomous card emulation without host processor involvement?
Yes. The PN7161B1HN/C100E supports Autonomous Card Emulation in T4T mode, allowing it to present pre-configured NDEF messages (e.g., transit pass, access credential) while the host MCU remains powered down. This is enabled via firmware configuration and requires only VBAT supply - VDD(PAD) is not needed. The IC wakes autonomously upon RF field detection and handles protocol stack execution independently.
What is the purpose of the ANT1 and ANT2 pins on PN7161B1HN/C100E?
The ANT1 and ANT2 pins on PN7161B1HN/C100E serve as dedicated wake-up antenna sense inputs. They monitor RF field presence independently of the main transceiver path, enabling the IC to exit Standby mode and initiate polling without host intervention. These pins support internal biasing and require no external components, making them ideal for ultra-low-power always-listening applications like smart locks or wearables.
Can PN7161B1HN/C100E operate with a 3.3 V-only supply, or does it require dual voltage rails?
The PN7161B1HN/C100E requires two distinct supply domains: VBAT (2.8–5.5 V) for RF and core logic, and VDD(PAD) (3.0–3.6 V) for the SPI interface. A single 3.3 V rail cannot satisfy both - VBAT must be ≥2.8 V and may be higher (e.g., 3.6–4.2 V from Li-ion). VDD(PAD) must be regulated to 3.3 V ±0.3 V. Using 3.3 V for both violates specification and risks undefined behavior in transmitter operation.
Is firmware update supported in-circuit for PN7161B1HN/C100E, and what interface is used?
Yes, in-circuit firmware updates are fully supported for PN7161B1HN/C100E via its SPI interface using the NCI 2.0 download protocol. The DWL_REQ pin initiates firmware download mode, and the process uses authenticated, encrypted image loading into internal EEPROM. Field updates to v12.50.11 or later are validated for ECP stability and XTAL startup robustness, with anti-tearing protection ensuring safe power-loss recovery.
PN7161B1HN/C100E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Standards:
- FeliCa, ISO 14443, ISO 15693, MIFARE, NFC
- Interface:
- SPI
- Voltage - Supply:
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Operating Temperature:
- -25°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-HVQFN (6x6)
PN7161B1HN/C100E FAQ
1.How can I place an order for PN7161B1HN/C100E through Aetrix?
Please submit a Request for Quotation (RFQ) for PN7161B1HN/C100E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN7161B1HN/C100E reliable?
The price and inventory of PN7161B1HN/C100E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN7161B1HN/C100E is usually 5 days.
3.What payment methods are accepted for PN7161B1HN/C100E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN7161B1HN/C100E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN7161B1HN/C100E?
PN7161B1HN/C100E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN7161B1HN/C100E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN7161B1HN/C100E?
For technical support, including PN7161B1HN/C100E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN7161B1HN/C100E requirements.
6.How does Aetrix verify that PN7161B1HN/C100E is sourced from the original manufacturer or authorized distributors?
All PN7161B1HN/C100E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN7161B1HN/C100E meets industry standards.
7.What is the process for return or replacement of PN7161B1HN/C100E?
All PN7161B1HN/C100E units undergo pre-shipment inspection (PSI). If there is an issue with PN7161B1HN/C100E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN7161B1HN/C100E part is unused and in its original packaging.
Return procedure for PN7161B1HN/C100E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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