NXP Semiconductors PN7360AUEV/C300Y
- Part No.:
- PN7360AUEV/C300Y
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 64-VFBGA
- Datasheet:
-
PN7360AUEV/C300Y.pdf
- Description:
- PN7360AUEV - NFC Cortex®
- Quantity:
- Payment:

- Shipping:

Inventory:4,000
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Product details
Overview
PN7360AUEV/C300Y from NXP Semiconductors is a 32-bit Arm Cortex-M0 NFC microcontroller with 80 kB Flash, 12 kB SRAM, and integrated 13.56 MHz contactless frontend supporting ISO/IEC 14443 A/B, NFC Forum Types 1–5, P2P, and card emulation - deployed in secure USB NFC readers and EMVCo-compliant payment terminals.
For engineers reviewing the PN7360AUEV/C300Y datasheet, PN7360AUEV/C300Y pinout, PN7360AUEV/C300Y application, or PN7360AUEV/C300Y equivalent, key selection criteria include VFBGA64 package compatibility, absence of contact interface (ISO/IEC 7816), lack of UART auxiliary interface, and 80 kB Flash memory constraint versus 160 kB variants in the same family.
Technical Context
The PN7360AUEV/C300Y implements a dedicated high-power NFC frontend with Adaptive Wave Control (AWC) and Dynamic Power Control (DPC), enabling EMV-level RF compliance without external active components. Its Cortex-M0 core runs at up to 20 MHz and integrates four general-purpose timers, CRC coprocessor, and random number generator.
It supports host interfaces including USB 2.0 full-speed, HSUART (up to 1.288 Mbit/s), SPI (up to 7 Mbit/s), and I²C (standard/fast/high-speed modes), but omits both contact smart card interface and ISO/IEC 7816-3&4 UART - distinguishing it from PN7462AUEV and PN7462AUHN variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M0, 20 MHz max - enables deterministic real-time NFC protocol handling with low interrupt latency. |
| Flash Memory | 80 kB - sufficient for lightweight NFC firmware stacks; half the capacity of PN7462-series parts. |
| SRAM | 12 kB - supports concurrent NFC stack operation, host interface buffering, and application logic. |
| Contactless Support | ISO/IEC 14443 A/B, NFC Forum Types 1–5, P2P initiator/target, card emulation - full RF protocol coverage at 13.56 MHz. |
| Operating Temp | −40 °C to +85 °C - qualified for industrial and consumer terminal environments. |
| Supply Voltage | VDDP(VBUS): 2.7–5.5 V - compatible with USB bus-powered and battery-operated designs. |
| Power Consumption | 12 µA in hard power-down mode - enables ultra-low-power wake-on-field detection in portable readers. |
Pinout & Package
VFBGA64 package (4.5 mm × 4.5 mm × 0.80 mm, SOT1307-2), ball-grid layout optimized for compact NFC reader PCBs with minimal RF trace length.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 (I2CM_SDA) | I²C master serial data I/O / GPIO13 | Host communication or general-purpose I/O; bidirectional with internal pull-up capability. |
| A2 (SPIM_MISO) | SPI master data input / GPIO20 | Receives data from peripheral SPI slaves; configurable as interrupt-capable GPIO. |
| A5 (VBUS) | Main supply voltage input | Primary power rail (2.7–5.5 V); powers digital core, USB PHY, and internal LDOs. |
| C7 (RST_N) | Active-low reset input | Asynchronous hardware reset; asserted low for ≥100 ns to initiate cold boot sequence. |
| E1 (DVDD) | Digital core logic supply | 1.8 V regulated output from internal LDO; powers CPU, memory, and digital peripherals. |
| G1 (ANT1) | NFC antenna connection | Load modulation node for card emulation and P2P passive target; requires matching network. |
| H1 (ANT2) | NFC antenna connection | Second antenna port for differential tuning; used with ANT1 to form balanced 13.56 MHz tank circuit. |
Key Features
| Feature | Design Value |
|---|---|
| EMVCo RF Compliance | Integrated high-power NFC frontend meets EMV contactless level 1 requirements without external amplifiers or matching ICs. |
| Low-Power Card Detection | Enables wake-from-sleep on RF field presence - critical for battery-powered point-of-sale terminals. |
| Dynamic Power Control (DPC) | Automatically adjusts RF output power based on coupling distance and tag response, improving interoperability. |
| Adaptive Wave Control (AWC) | Compensates for antenna detuning due to mechanical stress or nearby metal, maintaining stable link margin. |
| USB Mass Storage Bootloader | 40 kB ROM includes primary USB MSC bootloader - simplifies field firmware updates without JTAG debugger. |
Applications
| Secure USB NFC Reader | EMVCo Payment Terminal |
|---|---|
|
Use Scenario: Compact desktop or mobile USB-connected NFC reader for contactless card authentication and tokenized payments. IC Role / Device Role / Timing Role: Primary NFC controller executing ISO/IEC 14443 and NFC Forum protocols; handles RF framing, crypto offload, and host command translation. Use Value: Eliminates need for discrete NFC transceiver + MCU pairing; reduces BOM count and PCB area by 40% vs. two-chip solutions. |
Use Scenario: Integrated payment terminal with embedded NFC for tap-to-pay, supporting EMVCo Level 1 certification. IC Role / Device Role / Timing Role: Contactless transaction engine managing field generation, anti-collision, and secure element communication via SWP or I²C. Use Value: Meets EMV RF conformance out-of-box; avoids costly retesting when using external NFC ICs with variable RF performance. |
| Physical Access Control | Industrial Asset Tagging |
|
Use Scenario: Battery-powered door lock or gate controller reading NFC credentials in harsh indoor/outdoor environments. IC Role / Device Role / Timing Role: Standalone NFC initiator scanning for Type 4A/B tags; performs mutual authentication and session key derivation. Use Value: 12 µA hard power-down current extends coin-cell life to >2 years; −40 °C to +85 °C rating ensures reliability in unconditioned enclosures. |
Use Scenario: Ruggedized handheld scanner identifying NFC-enabled maintenance tags on factory equipment or HVAC units. IC Role / Device Role / Timing Role: High-sensitivity NFC reader supporting ISO/IEC 15693 and 18000-3 Mode 3 for long-range (~50 cm) asset interrogation. Use Value: Adaptive Range Control (ARC) maintains read range stability despite metal proximity - eliminating manual antenna retuning during deployment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7362AUEV | 160 kB Flash, same VFBGA64 package, no contact interface or ISO/IEC 7816 UART | Supports larger NFC middleware stacks and dual-application firmware (e.g., reader + secure element proxy) | Select when firmware size exceeds 80 kB or future-proofing for feature expansion is required. |
| PN7462AUEV | 160 kB Flash, VFBGA64, adds ISO/IEC 7816-3&4 UART interface for auxiliary smart card slot support | Enables dual-interface (contact + contactless) readers using TDA8026 slot extenders | Choose only if contact smart card extension is needed; otherwise PN7360AUEV/C300Y offers lower cost and simpler layout. |
Compared with PN7362AUEV and PN7462AUEV, PN7360AUEV/C300Y provides identical RF performance and package footprint but trades Flash capacity and optional contact interface for reduced unit cost and optimized BOM for pure contactless use cases.
Availability
PN7360AUEV/C300Y is available at Aetrix Electronics and suitable for secure USB NFC readers, EMVCo payment terminals, and physical access control systems requiring stable component supply across multi-year production cycles.
Supply support for PN7360AUEV/C300Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in NFC, RFID, and secure microcontrollers.
PN7360AUEV/C300Y belongs to the PN7462 family of NFC microcontrollers designed specifically for cost-sensitive, space-constrained contactless reader applications where integrated RF compliance and low-power operation are mandatory.
FAQ
What is the Flash memory size of PN7360AUEV/C300Y?
PN7360AUEV/C300Y contains 80 kB of on-chip Flash memory, confirmed in Table 3 (Ordering Information) and Section 4 (Quick Reference Data) of the PN7462 family datasheet Rev. 4.7. This is half the capacity of PN7462-series variants and constrains firmware complexity - PN7360AUEV/C300Y is intended for streamlined NFC reader implementations without extensive middleware layers.
Does PN7360AUEV/C300Y support contact smart card interfaces?
No, PN7360AUEV/C300Y does not include a contact smart card interface. As shown in Table 1 (Comparison of the PN7462 family members), it has "No" under both "Contact smart card reader" and "ISO/IEC 7816" columns. This distinguishes it from PN7462AUHN and PN7462AUEV, which integrate full ISO/IEC 7816-3&4 UART support for dual-interface readers.
What package type is used for PN7360AUEV/C300Y?
PN7360AUEV/C300Y uses the VFBGA64 package (4.5 mm × 4.5 mm × 0.80 mm, SOT1307-2), as specified in Table 3 (Ordering Information). This fine-pitch ball grid array enables high-density PCB layouts essential for compact USB NFC dongles and handheld readers, with thermal and electrical performance validated per JEDEC standards.
Which NFC protocols does PN7360AUEV/C300Y support?
PN7360AUEV/C300Y supports full NFC Forum tag types (1, 2, 3, 4A, 4B, 5), ISO/IEC 14443 A/B, ISO/IEC 15693, ISO/IEC 18000-3 Mode 3, P2P active/passive, and card emulation - all enabled by its integrated high-power contactless frontend, as detailed in Section 2.3 of the datasheet.
Is PN7360AUEV/C300Y pin-compatible with other PN7462 family members?
PN7360AUEV/C300Y shares the VFBGA64 pinout with PN7462AUEV and PN7362AUEV, as confirmed in Figures 8 and Table 5 (Pin description VFBGA64). However, functional pin mapping differs: PN7360AUEV/C300Y lacks contact interface pins (e.g., SCVDD, SAP, AUX1/AUX2) present on PN7462AUEV, making it not functionally interchangeable without PCB revision.
PN7360AUEV/C300Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 64-VFBGA
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- RFID Reader/Transponder
- Frequency:
- 13.56MHz
- Standards:
- FeliCa, ISO 14443, ISO 15693, ISO 18000-3, MIFARE, NFC
- Interface:
- I2C, SPI, UART, USB
- Voltage - Supply:
- 1.65V ~ 1.95V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VFBGA (4.5x4.5)
PN7360AUEV/C300Y FAQ
1.How can I place an order for PN7360AUEV/C300Y through Aetrix?
Please submit a Request for Quotation (RFQ) for PN7360AUEV/C300Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN7360AUEV/C300Y reliable?
The price and inventory of PN7360AUEV/C300Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN7360AUEV/C300Y is usually 5 days.
3.What payment methods are accepted for PN7360AUEV/C300Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN7360AUEV/C300Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN7360AUEV/C300Y?
PN7360AUEV/C300Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN7360AUEV/C300Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN7360AUEV/C300Y?
For technical support, including PN7360AUEV/C300Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN7360AUEV/C300Y requirements.
6.How does Aetrix verify that PN7360AUEV/C300Y is sourced from the original manufacturer or authorized distributors?
All PN7360AUEV/C300Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN7360AUEV/C300Y meets industry standards.
7.What is the process for return or replacement of PN7360AUEV/C300Y?
All PN7360AUEV/C300Y units undergo pre-shipment inspection (PSI). If there is an issue with PN7360AUEV/C300Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN7360AUEV/C300Y part is unused and in its original packaging.
Return procedure for PN7360AUEV/C300Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PN7360AUEV/C300Y Tags

-
SL2S2602FTBX
NXP Semiconductors

-
ST25DV04K-IER6S3
STMicroelectronics

-
ST25DV04K-IER6C3
STMicroelectronics

-
LXMSJZNCMD-217
Murata Electronics

-
NT3H2111W0FTTJ
NXP Semiconductors

-
NT3H2111W0FHKH
NXP Semiconductors

-
M24LR04E-RMC6T/2
STMicroelectronics

-
ST25DV04KC-JF6D3
STMicroelectronics

-
ST25DV64KC-IE6S3
STMicroelectronics
-
ST25DV64K-IER6T3
STMicroelectronics

-
NT3H2211W0FTTJ
NXP Semiconductors

-
NT3H2211W0FHKH
NXP Semiconductors
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