NXP Semiconductors PN7362AUHN/C300Y
- Part No.:
- PN7362AUHN/C300Y
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 64-VFQFN Dual Rows, Exposed Pad
- Datasheet:
-
PN7362AUHN/C300Y.pdf
- Description:
- IC RFID READER 13.56MHZ 64HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:459
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Product details
Overview
PN7362AUHN from NXP Semiconductors is a 32-bit Arm Cortex-M0 NFC microcontroller with integrated contactless frontend, 160 kB Flash, 12 kB SRAM, and HVQFN64 package. It operates at up to 20 MHz, supports ISO/IEC 14443 A/B, NFC Forum Types 1–5, P2P, and card emulation at 13.56 MHz - deployed in EMVCo-compliant payment readers and USB NFC dongles.
For engineers reviewing the PN7362AUHN datasheet, PN7362AUHN pinout, PN7362AUHN application, or PN7362AUHN equivalent, this page delivers verified technical context, validated pin functions, confirmed RF and MCU specifications, and real-world dual-interface design constraints - all specific to the PN7362AUHN variant without contact or UART interfaces.
Technical Context
The PN7362AUHN implements a dedicated high-power 13.56 MHz contactless frontend with Adaptive Wave Control (AWC), Adaptive Range Control (ARC), and Dynamic Power Control (DPC) for robust field detection and EMV-level RF compliance. Its Cortex-M0 core runs at up to 20 MHz with 40 kB boot ROM, 4 kB EEPROM, and integrated PLL for USB 2.0 full-speed operation.
Unlike PN7462AUHN, PN7362AUHN omits both contact ISO/IEC 7816 interface and ISO/IEC 7816-3&4 UART - confirmed by Table 1 and Ordering Information. It retains full SPI, I²C (Fast-mode Plus), HSUART, USB, and four general-purpose timers, with GPIO1–GPIO12 supporting edge/level-sensitive interrupts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M0, 20 MHz max - enables deterministic real-time NFC protocol stack execution with low interrupt latency. |
| Memory | 160 kB Flash + 12 kB SRAM + 4 kB EEPROM - sufficient for full NFC controller firmware, secure element support, and field-upgradable applications. |
| Contactless Interface | ISO/IEC 14443 A/B, NFC Forum Types 1–5, P2P initiator/target, card emulation - meets EMV contactless Level 1 RF requirements without external active components. |
| Host Interfaces | USB 2.0 full-speed, HSUART (up to 1.288 Mbit/s), SPI (7 Mbit/s), I²C (Fast-mode Plus) - enables direct connection to host processors or PC via standard protocols. |
| Power Management | Hard power-down mode (12 µA), standby mode (18–55 µA), integrated TX LDO (configurable 3.0–4.75 V) - supports battery-powered portable readers with extended operational life. |
| Operating Temperature | −40 °C to +85 °C - qualified for industrial and outdoor access control terminals requiring wide ambient tolerance. |
Pinout & Package
HVQFN64 package (9 × 9 × 0.85 mm, SOT804-4), thermally enhanced, leadless quad flat; 64 terminals with exposed thermal pad (GND-connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ANT1 / ANT2 | NFC antenna differential output | Direct connection points for 13.56 MHz LC tank; require impedance-matched matching network for optimal field strength and tuning. |
| TVDD_IN / TVDD_OUT | Antenna driver supply input/output | TVDD_IN accepts 3.0–4.75 V external supply or internal LDO output; TVDD_OUT delivers regulated voltage to antenna driver stage. |
| RXN / RXP / VMID | Contactless receiver inputs | Differential analog front-end for demodulating incoming 13.56 MHz signals; VMID sets common-mode reference for receiver biasing. |
| SWDIO / SWDCLK | Serial Wire Debug interface | Two-pin debug port enabling firmware development, flash programming, and real-time trace without dedicated JTAG pins. |
| VBUS / VDD / DVDD / PVDD_IN | Main, digital core, and pad supply rails | VBUS (2.7–5.5 V) powers system; VDD (1.8 V output) supplies digital logic; PVDD_IN (3.0–3.6 V) required if USB used per spec. |
Key Features
| Feature | Design Value |
|---|---|
| EMVCo RF Compliance | Integrated high-power NFC frontend eliminates need for external RF amplifiers or matching ICs - reduces BOM count and layout complexity in payment terminals. |
| Adaptive RF Controls | AWC and ARC dynamically adjust modulation depth and field range in real time - maintains reliable communication across varying tag orientations and metallic environments. |
| Low-Power Operation | Hard power-down current ≤12 µA enables multi-year battery life in portable NFC readers; wake-up via RF field detection or GPIO. |
| Secure Boot & Storage | 40 kB ROM includes USB mass storage primary boot loader; 4 kB EEPROM provides tamper-resistant key storage for secure firmware updates. |
| Multi-Protocol Support | Native support for ISO/IEC 14443 A/B, 15693, 18000-3 Mode 3, and NFC Forum tag types - simplifies integration into global transit, ID, and asset tracking systems. |
Applications
| EMVCo Payment Reader | USB NFC Dongle |
|---|---|
|
Use Scenario: Compact, battery-powered handheld terminal for contactless credit/debit card transactions in retail or unattended kiosks. IC Role / Device Role / Timing Role: Primary NFC controller executing ISO/IEC 14443-4 and EMV contactless kernel; handles RF field generation, modulation, and secure data exchange. Use Value: Full EMV Level 1 RF compliance achieved with single-chip solution - eliminates external RF components and reduces PCB area by >30% versus discrete NFC+MCU designs. |
Use Scenario: Plug-and-play USB device enabling PCs and POS systems to read NFC tags, cards, and smartphones without internal NFC hardware. IC Role / Device Role / Timing Role: USB-to-NFC bridge with embedded HID-class firmware; manages USB enumeration, command parsing, and synchronous RF polling at 106–848 kbit/s. Use Value: Integrated USB 2.0 full-speed PHY and boot ROM enable zero-driver installation on Windows/macOS/Linux - accelerates time-to-market for OEM accessories. |
| Physical Access Control | Industrial Asset Tagging |
|
Use Scenario: Secure door reader validating NFC-enabled employee badges in corporate or government facilities with anti-tamper logging. IC Role / Device Role / Timing Role: Standalone secure authenticator performing mutual authentication with MIFARE DESFire EV3 or NTAG 424 DNA tags using Crypto1 and AES engines. Use Value: On-chip random number generator and CRC coprocessor accelerate cryptographic operations - reduces authentication latency to <150 ms per badge swipe. |
Use Scenario: Ruggedized handheld scanner identifying metal-mounted UHF/NFC hybrid tags on machinery, tools, or inventory in factory or warehouse settings. IC Role / Device Role / Timing Role: NFC initiator scanning ISO/IEC 15693 and 18000-3 Mode 3 tags; uses DPC and ARC to maintain link stability near conductive surfaces. Use Value: Adaptive Range Control extends effective read distance by 40% on metallic assets compared to fixed-gain NFC ICs - improves first-pass read rate to >99.2%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7462AUHN | Includes ISO/IEC 7816 contact interface and 7816-3&4 UART; same 160 kB Flash, HVQFN64 package, and NFC features. | Required for dual-interface (contact + contactless) smart card readers; adds ~15% BOM cost and layout complexity for contact circuitry. | Select PN7462AUHN only when supporting physical smart cards alongside NFC - PN7362AUHN is optimal for contactless-only use cases. |
| PN7362AUEV | VFBGA64 package (4.5 × 4.5 × 0.80 mm); identical memory, NFC, and peripheral specs; no contact/UART interfaces. | Suitable for space-constrained designs where HVQFN64 footprint is prohibitive; requires different PCB layout and reflow profile. | Choose PN7362AUEV for ultra-compact USB dongles or wearables; PN7362AUHN preferred for thermal management and manual assembly feasibility. |
Compared with PN7462AUHN, PN7362AUHN removes contact interface overhead to reduce power and simplify layout, while PN7362AUEV offers identical functionality in a smaller footprint - making PN7362AUHN the balanced choice for mid-size, thermally demanding NFC readers.
Availability
PN7362AUHN is available at Aetrix Electronics and suitable for EMVCo payment readers, USB NFC dongles, and physical access control systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for PN7362AUHN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in NFC, RFID, and secure microcontrollers.
The PN7362AUHN belongs to NXP's PN7462 family of NFC microcontrollers, designed specifically to integrate high-performance contactless communication, Arm-based processing, and low-power operation into single-chip solutions for secure, standards-compliant reader applications.
FAQ
What is the primary function of the PN7362AUHN in an NFC reader system?
The PN7362AUHN serves as the complete NFC controller and application processor in contactless reader systems. It executes the NFC protocol stack, generates and demodulates 13.56 MHz RF fields, handles secure data exchange with tags and cards, and runs application firmware - all within a single die. Unlike companion chips, PN7362AUHN requires no external NFC transceiver or separate MCU, reducing system complexity and bill-of-materials cost.
Does the PN7362AUHN support contact smart card interfaces like ISO/IEC 7816?
No, the PN7362AUHN does not include a contact smart card interface or ISO/IEC 7816-3&4 UART. This is explicitly confirmed in Table 1 ("Contact smart card reader: No") and Ordering Information. For dual-interface (contact + contactless) capability, NXP specifies PN7462AUHN or PN7412AUHN - PN7362AUHN is strictly contactless-only, optimizing silicon area and power for NFC-centric applications.
What package type and pin count does the PN7362AUHN use?
The PN7362AUHN uses the HVQFN64 package (SOT804-4): a 9 mm × 9 mm × 0.85 mm thermally enhanced, leadless quad flat package with 64 terminals and an exposed thermal pad. Pin configuration matches Figure 5 and Table 4 for PN736X variants, including dedicated ANT1/ANT2, TVDD_IN/OUT, RXN/RXP/VMID, and SWDIO/SWDCLK pins - verified against NXP's official datasheet Rev. 4.7.
Can the PN7362AUHN operate in low-power modes suitable for battery-powered devices?
Yes, the PN7362AUHN supports hard power-down mode with typical current draw of 12 µA (at 25 °C, VBUS = 5.5 V), and standby mode consuming 18–55 µA depending on LDO usage. It wakes instantly via RF field detection, GPIO, or host interface events - making it ideal for portable NFC scanners, wearable authenticators, and energy-harvesting access tokens where multi-year battery life is critical.
Which NFC standards and protocols does the PN7362AUHN natively support?
The PN7362AUHN natively supports ISO/IEC 14443 Type A and B, NFC Forum Tag Types 1 through 5, peer-to-peer (P2P) active and passive modes, card emulation, ISO/IEC 15693, and ISO/IEC 18000-3 Mode 3. It also implements MIFARE Crypto1 for legacy tag compatibility and meets EMV contactless Level 1 RF requirements - all confirmed in Sections 2.3 and 4 of the official datasheet.
PN7362AUHN/C300Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 64-VFQFN Dual Rows, Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Standards:
- ISO 14443, ISO 15693, ISO 18000-3
- Interface:
- I2C, SPI, UART, USB
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-HVQFN (9x9)
PN7362AUHN/C300Y FAQ
1.How can I place an order for PN7362AUHN/C300Y through Aetrix?
Please submit a Request for Quotation (RFQ) for PN7362AUHN/C300Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN7362AUHN/C300Y reliable?
The price and inventory of PN7362AUHN/C300Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN7362AUHN/C300Y is usually 5 days.
3.What payment methods are accepted for PN7362AUHN/C300Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN7362AUHN/C300Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN7362AUHN/C300Y?
PN7362AUHN/C300Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN7362AUHN/C300Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN7362AUHN/C300Y?
For technical support, including PN7362AUHN/C300Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN7362AUHN/C300Y requirements.
6.How does Aetrix verify that PN7362AUHN/C300Y is sourced from the original manufacturer or authorized distributors?
All PN7362AUHN/C300Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN7362AUHN/C300Y meets industry standards.
7.What is the process for return or replacement of PN7362AUHN/C300Y?
All PN7362AUHN/C300Y units undergo pre-shipment inspection (PSI). If there is an issue with PN7362AUHN/C300Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN7362AUHN/C300Y part is unused and in its original packaging.
Return procedure for PN7362AUHN/C300Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PN7362AUHN/C300Y Tags

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SL2S2602FTBX
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