Nexperia USA Inc. PRTR5V0U4D,125
- Part No.:
- PRTR5V0U4D,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SC-74, SOT-457
- Datasheet:
-
PRTR5V0U4D,125.pdf
- Description:
- TVS DIODE 6TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:15,215
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Product details
Overview
PRTR5V0U4D from Nexperia is an ultra-low-capacitance quadruple rail-to-rail ESD protection diode array in SOT457 (SC-74/TSOP6) package, designed to protect four high-speed signal lines-such as USB 2.0 D+/D−, HDMI TMDS, or DVI data pairs-against IEC 61000-4-2 level 4 (±8 kV contact) ESD transients. It features 1 pF I/O-to-GND capacitance, integrated VCC-referenced clamping, and operates over 0–5.5 V input voltage range.
For engineers reviewing the PRTR5V0U4D datasheet, PRTR5V0U4D pinout, PRTR5V0U4D application, or PRTR5V0U4D equivalent, this device is selected for high-frequency interface protection where minimal signal distortion, sub-1 pF loading, and rail-to-rail clamping without external bias are critical-especially in USB 2.0, HDMI, and mobile peripheral designs.
Technical Context
The PRTR5V0U4D implements a quad-channel bidirectional rail-to-rail ESD clamp architecture with one dedicated low-leakage supply-line diode (pin 5 → pin 2), enabling effective transient suppression even when VCC is unpowered. Each I/O channel provides symmetrical clamping between its terminal and GND, with breakdown voltage of 6–9 V and reverse leakage ≤100 nA at 3 V.
Its 1 pF I/O-to-GND capacitance (measured per I/O pin to GND at 1 MHz, 0 V bias) ensures negligible signal integrity impact on 480 Mbps USB 2.0 differential pairs; the 40 pF VCC-to-GND capacitance supports stable supply decoupling during fast ESD events without compromising power rail noise performance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±8 kV per IEC 61000-4-2 contact discharge (pins 1/3/4/6 to GND or VCC) |
| I/O-to-GND Capacitance | 1 pF typical - preserves signal rise/fall times & impedance matching on USB/HDMI lines |
| Breakdown Voltage (VBR) | 6–9 V at 1 mA - ensures clamping activates before damage to downstream 3.3 V/5 V ICs |
| Reverse Leakage (IRM) | ≤100 nA at 3 V - avoids DC loading on high-impedance signal sources |
| Forward Voltage (VF) | 0.7 V typical - enables low-voltage clamping with minimal forward drop |
| Operating Voltage Range | 0–5.5 V - compatible with USB 2.0 (3.3 V), HDMI (3.3 V), and legacy 5 V interfaces |
| Junction Temp Limit | 150 °C - supports operation in compact, thermally constrained portable enclosures |
Pinout & Package
SOT457 (SC-74 / TSOP6) plastic surface-mount package: 6-pin, 1.7 mm × 3.1 mm footprint, 0.95 mm height, lead pitch 0.65 mm, gull-wing leads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O1 | First bidirectional ESD-protected signal line (e.g., USB D+) |
| 2 | GND | Common reference for all clamps; must be low-inductance connection to system ground plane |
| 3 | I/O2 | Second bidirectional ESD-protected signal line (e.g., USB D−) |
| 4 | I/O3 | Third bidirectional ESD-protected signal line (e.g., HDMI TMDS0+) |
| 5 | VCC | Supply reference for internal clamping diodes; enables enhanced clamping when powered |
| 6 | I/O4 | Fourth bidirectional ESD-protected signal line (e.g., HDMI TMDS0−) |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail bidirectional clamping | Clamps signals between VCC and GND without polarity dependency-enables use on AC-coupled differential pairs |
| Ultra-low 1 pF I/O capacitance | Maintains >400 MHz bandwidth on protected lines; meets USB 2.0 eye diagram mask requirements |
| Dedicated VCC-to-GND ESD diode | Ensures robust clamping on supply rail even during brown-out or unpowered states |
| Sub-100 nA reverse leakage | Prevents signal attenuation or DC offset drift in high-impedance sensor or analog front-end interfaces |
| SOT457 small-outline package | Enables placement adjacent to connectors with minimal PCB area (3.1 × 1.7 mm) and thermal mass |
Applications
| USB 2.0 Interface Protection | HDMI/DVI TMDS Line Protection |
|---|---|
Use Scenario: Protecting D+/D− differential pair and VBUS line on mini/micro-USB receptacles in smartphones and docking stations. IC Role / Device Role / Timing Role: ESD transient suppressor placed directly at connector, operating passively without power sequencing dependencies. Use Value: Prevents latch-up or gate oxide damage in USB PHY ICs during ±8 kV contact ESD events while adding <1 pF load per line. |
Use Scenario: Shielding TMDS clock and data channels on HDMI source devices (e.g., set-top boxes, GPUs) against board-level ESD coupling. IC Role / Device Role / Timing Role: Bidirectional rail-to-rail clamp ensuring signal integrity across 2.25 Gbps TMDS links without degrading edge rates. Use Value: Maintains HDMI compliance by limiting I/O capacitance to 1 pF and clamping transients within 1 ns response time. |
| Mobile Phone Camera Interface | LAN/WAN High-Speed Serial Link |
Use Scenario: Safeguarding MIPI D-PHY data lanes (CLKP/CLKN, DATAP/DATAN) between image sensor and SoC in compact camera modules. IC Role / Device Role / Timing Role: Low-capacitance ESD guard for 1–2 Gbps differential signaling; mounted within 3 mm of sensor connector. Use Value: Eliminates need for discrete RC filters while meeting IEC 61000-4-2 level 4 and preserving 100 Ω differential impedance. |
Use Scenario: Protecting 10/100/1000BASE-T PHY differential pairs (e.g., MDI pins) on Ethernet switch PCBs exposed to handling ESD. IC Role / Device Role / Timing Role: Front-end transient suppressor on unshielded twisted-pair interface, referenced to local GND and VCC rails. Use Value: Provides fail-safe clamping during hot-plug events without distorting 125 MHz Ethernet symbol timing or increasing jitter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor ESD9X5.0ST5G | Single-channel, 5.0 V standoff, 0.6 pF capacitance; no VCC pin or rail-to-rail clamping | Requires four separate devices for quad protection; lacks integrated supply-line clamp | Preferred only when lowest possible capacitance (<0.6 pF) is mandatory and board space allows discrete placement |
| Infineon ESD204-B1-02EL | Quad-channel, 1.2 pF I/O capacitance, 5.5 V working voltage, no VCC pin | Relies solely on GND-referenced clamping; less effective on powered lines during fast transients | Selected when cost sensitivity outweighs need for VCC-assisted clamping and 0.2 pF capacitance advantage is non-critical |
Compared with ESD9X5.0ST5G and ESD204-B1-02EL, PRTR5V0U4D uniquely combines quad integration, 1 pF loading, rail-to-rail clamping, and a dedicated VCC-referenced diode-making it optimal for space-constrained, high-speed interfaces requiring guaranteed clamping under both powered and unpowered conditions.
Availability
PRTR5V0U4D is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI/DVI TMDS line safeguarding, and mobile camera module ESD hardening requiring stable component supply and consistent parametric performance across production batches.
Supply support for PRTR5V0U4D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert headquartered in Nijmegen, Netherlands, specializing in high-performance, energy-efficient logic, analog, and ESD protection solutions for consumer, computing, and communications markets.
PRTR5V0U4D belongs to Nexperia's ultra-low-capacitance ESD protection portfolio, engineered specifically for high-speed digital interfaces where signal fidelity, board space, and robust transient immunity must coexist without trade-offs.
FAQ
Can PRTR5V0U4D be used without connecting VCC?
Yes. The device integrates a dedicated ESD diode from VCC to GND, but all four I/O channels operate as bidirectional rail-to-rail clamps independent of VCC connection. When VCC is unconnected, clamping occurs between each I/O pin and GND only-still providing ±8 kV IEC 61000-4-2 protection, though with slightly higher clamping voltage than when VCC is applied.
What is the maximum data rate supported on protected lines?
With 1 pF I/O-to-GND capacitance and rail-to-rail clamping, PRTR5V0U4D supports signal bandwidths exceeding 400 MHz. It has been validated in USB 2.0 (480 Mbps) and HDMI 1.4 (2.25 Gbps TMDS) applications, maintaining eye diagram compliance and jitter budgets when placed within 5 mm of the connector per layout guidelines in Nexperia's AN11122.
How does the VCC pin improve ESD performance?
The VCC pin connects to the system supply rail and enables lower-clamping-voltage operation by activating an additional internal diode path from I/O to VCC. This reduces dynamic clamping voltage by ~1.2 V compared to GND-only clamping, improving protection margin for 3.3 V or 5 V interface ICs during fast ESD pulses (e.g., IEC 61000-4-2 30 ns rise time).
Is PRTR5V0U4D automotive qualified?
No. Per Nexperia's revision history (v.3, April 2023), PRTR5V0U4D is explicitly designated as non-automotive qualified. It is not tested to AEC-Q200 stress requirements. For automotive applications, Nexperia recommends the PRTR5V0U4D-Q variant, which carries full AEC-Q200 qualification and extended temperature range (−40 °C to +125 °C).
PRTR5V0U4D,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SC-74, SOT-457
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- -
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- -
- Capacitance @ Frequency:
- 1pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSOP
PRTR5V0U4D,125 FAQ
1.How can I place an order for PRTR5V0U4D,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for PRTR5V0U4D,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PRTR5V0U4D,125 reliable?
The price and inventory of PRTR5V0U4D,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PRTR5V0U4D,125 is usually 5 days.
3.What payment methods are accepted for PRTR5V0U4D,125?
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PRTR5V0U4D,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PRTR5V0U4D,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PRTR5V0U4D,125?
For technical support, including PRTR5V0U4D,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PRTR5V0U4D,125 requirements.
6.How does Aetrix verify that PRTR5V0U4D,125 is sourced from the original manufacturer or authorized distributors?
All PRTR5V0U4D,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PRTR5V0U4D,125 meets industry standards.
7.What is the process for return or replacement of PRTR5V0U4D,125?
All PRTR5V0U4D,125 units undergo pre-shipment inspection (PSI). If there is an issue with PRTR5V0U4D,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PRTR5V0U4D,125 part is unused and in its original packaging.
Return procedure for PRTR5V0U4D,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PRTR5V0U4D,125 Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

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D5V0H1B2LP-7B
Diodes Incorporated

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D5V0P1B2LP-7B
Diodes Incorporated

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DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

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DESD5V0U1BB-7
Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
Nexperia USA Inc.

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DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

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D5V0L1B2WS-7
Diodes Incorporated
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