Nexperia USA Inc. PUSB2X4DH
- Part No.:
- PUSB2X4DH
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SC-74, SOT-457
- Datasheet:
-
PUSB2X4DH.pdf
- Description:
- TVS DIODE 4.3VC 6TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:9,518
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Product details
Overview
PUSB2X4DH from Nexperia is a 4-channel ESD protection diode array for USB 2.0 high-speed data lines, featuring rail-to-rail clamping, ±12 kV IEC 61000-4-2 contact ESD immunity, and ultra-low line capacitance of 0.85 pF max per channel in SOT457 (SC-74) package. It protects D+ and D− signal pairs plus two additional high-speed lines in portable and embedded host/device ports.
For engineers reviewing the PUSB2X4DH datasheet, PUSB2X4DH pinout, PUSB2X4DH application, or PUSB2X4DH equivalent, key selection criteria include line capacitance impact on signal integrity, clamping voltage under 4.8 A transient, dynamic resistance below 0.48 Ω, and compatibility with 5 V tolerant USB 2.0 PHY interfaces.
Technical Context
This device implements a snap-back clamping structure with negative dynamic resistance, enabling low clamping voltage (4.3 V positive / −2.7 V negative at specified IPP) during ESD transients. Its four protected channels are individually configured for bidirectional rail-to-rail clamping between VCC and GND.
Each channel exhibits typ. 0.7 pF line capacitance at 1 MHz and 0 V bias, dropping to 0.6 pF at 2.5 V bias - critical for preserving USB 2.0 480 Mbps eye diagram integrity. The non-connected Pin 5 isolates internal substrate coupling to minimize crosstalk.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±12 kV contact per IEC 61000-4-2 Level 4 - ensures robust system-level ESD immunity without external TVS cascading |
| Line Capacitance | 0.85 pF max per channel at 1 MHz, 0 V - preserves USB 2.0 signal rise/fall times and minimizes insertion loss |
| Clamping Voltage | 4.3 V (positive), −2.7 V (negative) at IPP = 4.8/−5.2 A - limits downstream PHY stress below 5.5 V absolute max rating |
| Breakdown Voltage | 6–9 V at 1 mA - sets reliable snap-back initiation margin above 5 V USB supply rails |
| Dynamic Resistance | 0.48 Ω (pos), 0.34 Ω (neg) - enables fast energy shunting with minimal IR drop during ESD pulse |
| Reverse Leakage | ≤1 µA per channel at 5 V - prevents DC loading of high-impedance USB receiver inputs |
Pinout & Package
Package: SOT457 (SC-74), 6-pin surface-mount plastic package, 3.0 × 1.7 mm footprint, 0.95 mm height, pin pitch 0.95 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Protected I/O (Channel A) | ESD-clamped signal line connected to USB D+ or auxiliary high-speed data path |
| 2 | Ground | Low-inductance return path for all four clamping diodes; must be tied to clean system ground plane |
| 3 | Protected I/O (Channel B) | ESD-clamped signal line connected to USB D− or second differential pair |
| 4 | Protected I/O (Channel C) | Third independent protected line for auxiliary signals (e.g., ID, VBUS sense, or sideband) |
| 5 | No Connect (NC) | Internally unconnected; must remain floating - no PCB trace or thermal pad connection |
| 6 | Protected I/O (Channel D) | Fourth protected line supporting dual-port or multi-lane interface extension beyond standard USB 2.0 |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail clamping | Diodes clamp between VCC and GND on all four channels - eliminates need for external VCC decoupling capacitors |
| Ultra-low capacitance | 0.85 pF max per channel - meets USB 2.0 eye mask requirements up to 480 Mbps with <1% jitter contribution |
| Snap-back architecture | Negative dynamic resistance reduces clamping voltage by >30% vs. standard TVS - lowers stress on PHY ESD structures |
| IEC 61000-4-2 Level 4 compliance | Validated ±12 kV contact discharge - satisfies end-equipment CE/UL/CCC certification test plans without derating |
| SC-74 compact footprint | 3.0 × 1.7 mm body - fits within tight spacing constraints of mini-USB, micro-USB, and USB-C port layouts |
Applications
| USB 2.0 Host Port Protection | USB 2.0 Device Port Protection |
|---|---|
|
Use Scenario: Protecting upstream-facing USB ports on notebooks, motherboards, and docking stations against user-handling ESD events. IC Role / Device Role / Timing Role: Front-end ESD suppressor placed immediately before USB PHY transceiver input pins. Use Value: Prevents latch-up or permanent damage to integrated USB PHY while maintaining <0.5 dB insertion loss at 240 MHz. |
Use Scenario: Securing downstream-facing USB ports on peripherals such as external HDDs, webcams, and keyboards. IC Role / Device Role / Timing Role: Bi-directional signal-line protector for D+/D− differential pair and auxiliary control lines. Use Value: Enables full ±12 kV IEC 61000-4-2 compliance without degrading signal integrity or requiring layout rework. |
| Set-Top Box Interface Protection | Game Console Peripheral Port |
|
Use Scenario: Shielding HDMI-CEC or USB-based firmware update ports in consumer AV equipment exposed to frequent cable insertion/removal. IC Role / Device Role / Timing Role: Multi-line ESD guard for mixed-signal interfaces sharing ground with analog video/audio subsystems. Use Value: Isolates ESD transients from sensitive audio DACs and video timing controllers via low-coupling SC-74 package design. |
Use Scenario: Hardening controller sync, power negotiation, and accessory enumeration lines in game console USB hubs. IC Role / Device Role / Timing Role: Four-channel protector covering D+, D−, VBUS sense, and ID pin in USB On-The-Go configurations. Use Value: Supports hot-plug reliability across 10,000+ connect/disconnect cycles while maintaining <10 ps inter-pair skew. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR (TI) | 2-channel, 0.75 pF/channel, ±8 kV IEC 61000-4-2, SOT-553 package | Limited to dual-line protection; lacks Channel C/D for auxiliary signal coverage | Select when only D+/D− protection is required and board space permits smaller 5-pin package |
| ESD56081D05 (ON Semi) | 4-channel, 0.9 pF/channel, ±15 kV air discharge, SOT-23-6 package | Higher capacitance increases USB 2.0 jitter; larger SOT-23-6 footprint requires more PCB area | Prefer for environments demanding higher air-discharge margin where signal integrity tolerance allows +0.05 pF penalty |
Compared with TPD2E001DRYR and ESD56081D05, PUSB2X4DH delivers optimal balance of 4-channel coverage, 0.85 pF capacitance ceiling, and compact SC-74 layout - making it the preferred choice for space-constrained USB 2.0 designs requiring full differential + auxiliary line protection.
Availability
PUSB2X4DH is available at Aetrix Electronics and suitable for USB 2.0 host ports, portable device peripheral interfaces, and set-top box connectivity modules requiring stable component supply across long-life industrial and consumer programs.
Supply support for PUSB2X4DH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in ESD protection, MOSFETs, and bipolar transistors.
PUSB2X4DH belongs to Nexperia's USB-focused ESD protection portfolio, engineered specifically for high-speed serial interface integrity and system-level EMC compliance in cost-sensitive consumer and computing applications.
FAQ
What is the maximum recommended operating voltage for PUSB2X4DH?
The device supports continuous operation up to +5.5 V on all protected I/O pins, with breakdown voltage guaranteed between 6 V and 9 V at 1 mA. This provides ≥0.5 V margin above standard 5 V USB VBUS and PHY supply rails, ensuring safe operation during normal signaling without triggering snap-back conduction.
Can Pin 5 be grounded or left unconnected?
Pin 5 is explicitly designated as No Connect (NC) in the datasheet and must remain unconnected on the PCB. Grounding or routing this pin risks internal substrate coupling, increased crosstalk between channels, and potential degradation of ESD performance - confirmed by Nexperia's package outline and pinning diagrams.
How does the snap-back behavior affect circuit design?
Snap-back reduces clamping voltage during ESD events but requires avoiding sustained DC overvoltage (>9 V) on protected lines, as this could hold the device in low-impedance state and cause thermal failure. Designers must ensure USB PHY drivers never exceed 5.5 V absolute maximum ratings under fault conditions.
Is PUSB2X4DH qualified for automotive applications?
No - the datasheet explicitly states this is a non-automotive qualified product. It lacks AEC-Q200 qualification, automotive-grade temperature cycling validation, and extended lifetime testing. For automotive USB ports, Nexperia offers separate AEC-Q200 qualified variants such as PUSB2X4DH-Q.
PUSB2X4DH Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SC-74, SOT-457
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- -
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 4.3V (Typ)
- Current - Peak Pulse (10/1000µs):
- 4.8A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.7pF @ 1MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSOP
PUSB2X4DH FAQ
1.How can I place an order for PUSB2X4DH through Aetrix?
Please submit a Request for Quotation (RFQ) for PUSB2X4DH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PUSB2X4DH reliable?
The price and inventory of PUSB2X4DH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PUSB2X4DH is usually 5 days.
3.What payment methods are accepted for PUSB2X4DH?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PUSB2X4DH transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PUSB2X4DH?
PUSB2X4DH orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PUSB2X4DH order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PUSB2X4DH?
For technical support, including PUSB2X4DH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PUSB2X4DH requirements.
6.How does Aetrix verify that PUSB2X4DH is sourced from the original manufacturer or authorized distributors?
All PUSB2X4DH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PUSB2X4DH meets industry standards.
7.What is the process for return or replacement of PUSB2X4DH?
All PUSB2X4DH units undergo pre-shipment inspection (PSI). If there is an issue with PUSB2X4DH, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PUSB2X4DH part is unused and in its original packaging.
Return procedure for PUSB2X4DH:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PUSB2X4DH Tags

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Nexperia USA Inc.

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