Texas Instruments RF-HDT-SJLC-G0
- Part No.:
- RF-HDT-SJLC-G0
- Manufacturer:
- Texas Instruments
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- Die
- Datasheet:
-
RF-HDT-SJLC-G0.pdf
- Description:
- IC RFID TRANSP 13.56MHZ WAFER
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
RF-HDT-SJLC-G0 from Texas Instruments is a 13.56 MHz ISO/IEC 15693- and ISO/IEC 18000-3-compliant passive RFID transponder IC with 2 kbit EEPROM memory organized in 64 programmable blocks, factory-programmed 64-bit UID, and dual lock capability (user + factory). It operates without integrated resonance capacitor and requires external antenna tuning for HF RFID smart label inlays used in logistics, asset tagging, and access control.
For engineers reviewing the RF-HDT-SJLC-G0 datasheet, RF-HDT-SJLC-G0 pinout, RF-HDT-SJLC-G0 application, or RF-HDT-SJLC-G0 equivalent, this page delivers verified mechanical die dimensions (1296 × 1116 μm), bump specification (Ni/Au, 25 μm height), electrical characteristics (50 μA operating current, 10-year data retention), and ISO-compliant command set including TI-custom Write_2_Blocks and Lock_2_Blocks.
Technical Context
The RF-HDT-SJLC-G0 implements full-duplex communication at 13.56 MHz using ASK downlink (10–30% or 100% modulation) and ASK/FSK uplink with high/low data rates. It supports all ISO 15693 parameter combinations and frame-synchronized, CRC-secured transactions.
Its memory architecture includes 2 kbit user EEPROM (64 × 32-bit blocks), factory-programmed UID and configuration blocks, and two independent lock bits per block-enabling irreversible user locking and factory locking of critical data such as IC version and physical memory info.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Frequency | 13.56 MHz carrier - enables compliance with global HF RFID regulations and interoperability with ISO 15693 readers. |
| User Memory Size | 2 kbit (64 blocks × 32 bits) - supports storage of item-specific data like origin/destination, pallet ID, and route history in supply chain applications. |
| Data Retention | 10 years at 55°C - ensures long-term reliability of stored data in industrial and logistics environments. |
| Write/Erase Endurance | 100,000 cycles - allows repeated reprogramming during asset lifecycle management and dynamic labeling workflows. |
| Die Dimensions | 1296 × 1116 μm ±15 μm - defines minimum inlay footprint and enables high-density wafer-level packaging for cost-effective smart label production. |
| Bump Height | 25 μm ±10% Ni/Au - ensures robust flip-chip bonding to flexible antenna substrates in high-volume inlay manufacturing. |
| ESD Immunity | HBM 3.0 kV (ANT1/ANT2), 2.0 kV (TDAT/GND) - provides handling robustness during wafer sawing, die attach, and inlay assembly. |
Pinout & Package
RF-HDT-SJLC-G0 is supplied as a bare die on sawn wafers with Ni/Au bumps and no encapsulation. Package mapping confirms it is a wafer-level chip-scale package (WLCSP) with 8 terminals: ANT1, ANT2, TDI, VCCA, TDO, GND, and two additional ANT2 pads for antenna connection redundancy and impedance matching flexibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ANT1 | Antenna input terminal 1 | Primary RF coupling node; must be connected to external antenna trace with precise LC resonance tuning (no internal capacitor). |
| ANT2 (×3) | Antenna input terminal 2 | Three dedicated ANT2 pads (Pads 5, 6, 8) enable multi-point antenna attachment for improved impedance matching and mechanical stability on foil or PET substrates. |
| TDI | Test Data Input | Serial programming interface for wafer-level functional test; not used in final inlay operation. |
| VCCA | Test power supply | Test-only voltage supply pad; inactive in field operation; isolated from RF power harvesting path. |
| TDO | Test Data Output | Serial test response output; enables automated wafer probe testing prior to dicing and inlay assembly. |
| GND | Ground reference | Substrate ground connection; electrically tied to VSS potential; critical for RF return path integrity and ESD discharge routing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Block Locking (User + Factory) | Each 32-bit block supports independent U-lock (field-programmable) and F-lock (factory-set), enabling secure separation of user-configurable and immutable firmware/data regions. |
| TI-Custom Command Set | Write_2_Blocks and Lock_2_Blocks commands reduce transaction count by 50% vs. standard ISO 15693 for adjacent block operations, accelerating bulk inlay encoding in high-speed label converters. |
| Full ISO 15693 Parameter Support | Simultaneous compatibility with all ASK/FSK uplink modes and 1-of-4 / 1-of-256 downlink coding ensures interoperability across global reader ecosystems without mode negotiation overhead. |
| Collision Resolution (Anticollision) | Hardware-accelerated inventory protocol enables simultaneous identification of >100 tags within reader field, reducing warehouse pallet scan time to sub-second levels. |
| Factory-Programmed UID | 64-bit globally unique identifier permanently laser-programmed and locked at wafer test, eliminating post-assembly UID programming steps and ensuring traceability from silicon to finished label. |
Applications
| Asset Tracking in Industrial Warehouses | Reusable Container Management |
|---|---|
|
Use Scenario: Metal-rich warehouse environments where pallets and bins move through chokepoints equipped with fixed HF RFID readers. IC Role / Device Role / Timing Role: Passive transponder IC harvesting RF energy from reader field to power EEPROM read/write and transmit UID + payload via ASK-modulated uplink. Use Value: 10-year data retention and 100,000 write cycles support multi-year reuse of containers without memory degradation, while dual lock prevents tampering with calibration or ownership data. |
Use Scenario: Closed-loop logistics of plastic totes between distribution centers and retail stores, requiring durable, low-cost, printable labels. IC Role / Device Role / Timing Role: Bare-die RFID IC embedded in adhesive-backed inlay, bonded to tote surface; responds to ISO 15693 inventory commands within 200 ms. Use Value: 1296 × 1116 μm die size enables compact inlay design compatible with narrow-format thermal printers, and Ni/Au bumps ensure reliable bonding to polyester substrate under thermal cycling. |
| Airline Baggage Handling | Electronic Access Badges |
|
Use Scenario: High-throughput baggage sortation systems scanning hundreds of bags per minute on conveyor belts. IC Role / Device Role / Timing Role: Transponder IC providing collision-resistant UID broadcast and DSFID-based routing data to gate readers at merge points. Use Value: Full ISO 15693 anticollision and frame-synchronized CRC allow deterministic identification of overlapping tags at speeds up to 2 m/s, reducing misreads below 0.01%. |
Use Scenario: Secure employee badges issued for facility entry, requiring tamper-proof identity storage and fast proximity authentication. IC Role / Device Role / Timing Role: Contactless transponder IC storing encrypted AFI and DSFID values; responds to addressed read commands in <15 ms. Use Value: Factory-locked UID and optional AFI/DSFID locking prevent cloning or unauthorized reprogramming, meeting ISO/IEC 15693 security requirements for physical access systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar passive HF RFID transponder IC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP ICODE SLI-S | Integrated 27 pF resonance capacitor; 1 kbit EEPROM; no TI-custom commands; 5-year data retention. | Lower-cost inlays where external capacitor omission simplifies antenna design but reduces tuning flexibility. | Choose when antenna design resources are limited and 5-year retention suffices for disposable label use cases. |
| STMicroelectronics ST25DV02K | I²C + RF dual-interface; 2 kbit EEPROM; 40-year data retention; requires active power for I²C mode. | Hybrid applications needing both contactless interrogation and wired configuration (e.g., field-updatable access credentials). | Choose only if dual-interface functionality is required; RF-HDT-SJLC-G0 offers superior cost and simplicity for pure passive HF RFID. |
Compared with NXP ICODE SLI-S and STMicroelectronics ST25DV02K, RF-HDT-SJLC-G0 delivers higher write endurance (100k vs. 10k cycles), wafer-level bump geometry optimized for high-speed inlay lamination, and TI-proprietary multi-block commands that cut encoding time by half-making it optimal for high-volume, cost-sensitive smart label production.
Availability
RF-HDT-SJLC-G0 is available at Aetrix Electronics and suitable for industrial asset tracking, reusable container management, airline baggage handling, and electronic access badge applications requiring stable component supply across multi-year production programs.
Supply support for RF-HDT-SJLC-G0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in RFID and wireless identification solutions.
RF-HDT-SJLC-G0 belongs to TI's Tag-it HF-I Plus product line, designed specifically for high-reliability, high-volume passive HF RFID inlay manufacturing in logistics, transportation, and secure identification markets.
FAQ
What is the primary function of the RF-HDT-SJLC-G0 in an RFID system?
The RF-HDT-SJLC-G0 is a passive 13.56 MHz transponder IC that harvests energy from a reader's RF field to power its 2 kbit EEPROM, store and retrieve data via ISO/IEC 15693-compliant commands, and transmit responses using ASK or FSK uplink modulation. It serves as the core silicon element in smart labels for identification and data logging without batteries or external power.
Does the RF-HDT-SJLC-G0 include an integrated resonance capacitor?
No, the RF-HDT-SJLC-G0 does not include an integrated resonance capacitor. As stated in the Reference Guide, it relies solely on internal parasitic capacitance and requires external antenna tuning-either through added discrete capacitance or antenna geometry-to achieve proper LC resonance at 13.56 MHz for reliable RF coupling.
How is memory protection implemented on the RF-HDT-SJLC-G0?
The RF-HDT-SJLC-G0 implements two independent lock mechanisms per 32-bit block: User Lock (U), which can be set in-field to prevent further writes, and Factory Lock (F), which is programmed and permanently locked during wafer test. Once either lock bit is set, it cannot be reset-ensuring irreversible protection of UID, configuration data, or user-defined payloads.
What are the mechanical dimensions and bump specifications of the RF-HDT-SJLC-G0 die?
The RF-HDT-SJLC-G0 die measures 1296 × 1116 μm ±15 μm (excluding scribe line) with Ni/Au bumps at 25 μm ±10% height. It features eight terminals: three ANT2 pads (Pads 5, 6, 8), two ANT1 pads (Pads 1, 8), plus TDI, VCCA, TDO, and GND-optimized for flip-chip bonding onto flexible antenna substrates in high-yield inlay production.
Can the RF-HDT-SJLC-G0 be used in metal-mount RFID applications?
The RF-HDT-SJLC-G0 is not inherently metal-mount capable due to its lack of integrated ferrite shielding or tuned ground plane. Successful deployment on metal requires custom antenna design-including dielectric spacers, ground-plane isolation, or impedance-matching networks-to mitigate eddy current losses and detuning effects. Reference designs for metal-mount variants are not provided for RF-HDT-SJLC-G0 in the official documentation.
RF-HDT-SJLC-G0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- Tag-It
- Package/Case:
- Die
- Packaging:
- Box
- Product Status:
- Obsolete
- Type:
- RFID Transponder
- Frequency:
- 13.56MHz
- Standards:
- ISO 15693, ISO 18000-3
- Interface:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- Wafer
RF-HDT-SJLC-G0 FAQ
1.How can I place an order for RF-HDT-SJLC-G0 through Aetrix?
Please submit a Request for Quotation (RFQ) for RF-HDT-SJLC-G0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for RF-HDT-SJLC-G0 reliable?
The price and inventory of RF-HDT-SJLC-G0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for RF-HDT-SJLC-G0 is usually 5 days.
3.What payment methods are accepted for RF-HDT-SJLC-G0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for RF-HDT-SJLC-G0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for RF-HDT-SJLC-G0?
RF-HDT-SJLC-G0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your RF-HDT-SJLC-G0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for RF-HDT-SJLC-G0?
For technical support, including RF-HDT-SJLC-G0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your RF-HDT-SJLC-G0 requirements.
6.How does Aetrix verify that RF-HDT-SJLC-G0 is sourced from the original manufacturer or authorized distributors?
All RF-HDT-SJLC-G0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that RF-HDT-SJLC-G0 meets industry standards.
7.What is the process for return or replacement of RF-HDT-SJLC-G0?
All RF-HDT-SJLC-G0 units undergo pre-shipment inspection (PSI). If there is an issue with RF-HDT-SJLC-G0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The RF-HDT-SJLC-G0 part is unused and in its original packaging.
Return procedure for RF-HDT-SJLC-G0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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