Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Vishay Siliconix SI3454CDV-T1-E3

Name: SI3454CDV-T1-E3
Brand: Vishay Siliconix
SKU: SI3454CDV-T1-E3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI3454CDV-T1-E3

Manufacturer:: Vishay Siliconix

Category:: FETs, MOSFETs

Package:: SOT-23-6 Thin, TSOT-23-6

Datasheet:: SI3454CDV-T1-E3.pdf

Description:: MOSFET N-CH 30V 4.2A 6TSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:5,299

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI3454CDV-T1-E3 from Vishay Siliconix is a N-channel 30 V (D-S) TrenchFET® Power MOSFET in TSOP-6 package, with R_DS(on) = 0.050 Ω at V_GS = 10 V, continuous drain current of 4.2 A at T_C = 25 °C, and total gate charge of 5.3 nC (typ). It serves as a high-efficiency load switch in notebook PC power rails.

For engineers reviewing the SI3454CDV-T1-E3 datasheet, SI3454CDV-T1-E3 pinout, SI3454CDV-T1-E3 application, or SI3454CDV-T1-E3 equivalent, key selection criteria include its low R_DS(on) at 4.5 V drive, 100% R_g tested gate resistance, halogen-free and RoHS-compliant construction, and thermal performance on FR4 board.

Technical Context

This MOSFET uses trench-based silicon architecture to achieve low conduction loss and fast switching. Its gate threshold voltage (1–3 V) enables compatibility with 3.3 V and 5 V logic-level drivers, and its body diode exhibits t_rr = 11.5 ns (typ) and Q_rr = 5 nC (typ), supporting synchronous rectification in DC-DC converters.

The device is characterized for operation from −55 °C to +150 °C junction temperature, with R_thJA = 80 °C/W (typ) on 1" × 1" FR4 and R_thJF = 70 °C/W (typ) to the drain foot-enabling direct thermal coupling to PCB copper pour for enhanced power handling in space-constrained notebook designs.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	30 V - Maximum blocking voltage compatible with 3.3 V/5 V system rails and USB PD input stages.
R_DS(on)	0.050 Ω at V_GS = 10 V - Enables <150 mW conduction loss at 4.2 A, critical for thermally constrained notebook load switches.
I_D (cont)	4.2 A at T_C = 25 °C - Supports sustained current delivery in high-density portable power domains.
Q_g	5.3 nC (typ) at V_GS = 10 V - Reduces gate drive power and switching transition time in high-frequency PWM control.
V_GS(th)	1–3 V - Ensures reliable turn-on with standard logic-level microcontroller GPIOs without level-shifting.
t_rr	11.5 ns (typ) - Minimizes reverse recovery losses when used in buck converter freewheeling paths.

Pinout & Package

TSOP-6 surface-mount package (3 mm × 2.85 mm), lead (Pb)-free, halogen-free per IEC 61249-2-21. Drain terminals are pins 1, 2, 5, and 6; source is pin 3; gate is pin 4.

Pin/Terminal	Circuit Role	Design Meaning
1, 2, 5, 6	Drain (D)	High-current output node; electrically and thermally connected to exposed drain pad for PCB heat sinking.
3	Source (S)	Power return path; tied to ground or low-side reference; forms body diode anode.
4	Gate (G)	Control input; requires ≤±20 V drive; 100% R_g tested for consistent switching timing.

Key Features

Feature	Design Value
TrenchFET® architecture	Delivers lower R_DS(on) per die area than planar MOSFETs, enabling compact 3 mm × 2.85 mm footprint without sacrificing current rating.
100% R_g tested	Guarantees gate resistance between 0.44 Ω and 4.4 Ω, ensuring predictable turn-on/turn-off timing across production lots.
Low Q_gd/Q_g ratio	0.8 nC / 5.3 nC ≈ 15% - Reduces Miller effect, improving noise immunity and enabling stable operation in high-dV/dt environments.
Body diode with fast t_rr	11.5 ns typical reverse recovery time - Allows use in synchronous-buck topologies without external Schottky catch diodes.

Applications

Notebook PC Load Switch	USB-C Power Delivery Input Stage
Use Scenario: Selective power gating of GPU or SSD subsystems during sleep mode to meet ACPI S3/S4 leakage targets. IC Role / Device Role / Timing Role: Low-side load switch controlling 3.3 V or 5 V domain enable/disable with <1 µA gate leakage. Use Value: R_DS(on) = 0.050 Ω limits voltage drop to <210 mV at 4.2 A, preserving rail regulation while minimizing self-heating on thin FR4 layers.	Use Scenario: Input protection and hot-swap control for 20 V USB-C PD sources feeding internal DC-DC converters. IC Role / Device Role / Timing Role: High-side or low-side power path switch with overcurrent detection interface and fast fault shutdown response. Use Value: V_DS = 30 V rating provides 10 V margin above 20 V PD max, and t_rr = 11.5 ns prevents shoot-through during dynamic load transients.
Portable SSD Power Rail Control	Embedded System Battery Backup Switch
Use Scenario: Isolating NVMe controller power from main 3.3 V rail during suspend-to-RAM to reduce standby current. IC Role / Device Role / Timing Role: Logic-level controlled power switch with minimal quiescent current and fast enable/disable transitions. Use Value: V_GS(th) = 1–3 V ensures full enhancement using 3.3 V GPIOs; I_DSS ≤ 1 µA at 30 V preserves battery life over multi-week storage.	Use Scenario: Seamless switchover between main supply and backup coin cell or supercapacitor in real-time clock modules. IC Role / Device Role / Timing Role: Bidirectional load switch managing forward and reverse current paths with low forward voltage drop. Use Value: Body diode V_SD = 0.8–1.2 V at 3.1 A enables efficient reverse conduction during backup activation without external diode.

Notebook PC Load Switch

USB-C Power Delivery Input Stage

Use Scenario: Selective power gating of GPU or SSD subsystems during sleep mode to meet ACPI S3/S4 leakage targets.

IC Role / Device Role / Timing Role: Low-side load switch controlling 3.3 V or 5 V domain enable/disable with <1 µA gate leakage.

Use Value: R_DS(on) = 0.050 Ω limits voltage drop to <210 mV at 4.2 A, preserving rail regulation while minimizing self-heating on thin FR4 layers.

Use Scenario: Input protection and hot-swap control for 20 V USB-C PD sources feeding internal DC-DC converters.

IC Role / Device Role / Timing Role: High-side or low-side power path switch with overcurrent detection interface and fast fault shutdown response.

Use Value: V_DS = 30 V rating provides 10 V margin above 20 V PD max, and t_rr = 11.5 ns prevents shoot-through during dynamic load transients.

Portable SSD Power Rail Control

Embedded System Battery Backup Switch

Use Scenario: Isolating NVMe controller power from main 3.3 V rail during suspend-to-RAM to reduce standby current.

IC Role / Device Role / Timing Role: Logic-level controlled power switch with minimal quiescent current and fast enable/disable transitions.

Use Value: V_GS(th) = 1–3 V ensures full enhancement using 3.3 V GPIOs; I_DSS ≤ 1 µA at 30 V preserves battery life over multi-week storage.

Use Scenario: Seamless switchover between main supply and backup coin cell or supercapacitor in real-time clock modules.

IC Role / Device Role / Timing Role: Bidirectional load switch managing forward and reverse current paths with low forward voltage drop.

Use Value: Body diode V_SD = 0.8–1.2 V at 3.1 A enables efficient reverse conduction during backup activation without external diode.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel load switch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
DMN3026LSD-13	R_DS(on) = 0.035 Ω at V_GS = 10 V; SO-8 package; higher I_D = 6.5 A; no 100% R_g test.	Larger footprint; better for higher-current rails but less suitable for ultra-thin notebook edge zones.	Choose when board space allows SO-8 and lower R_DS(on) is prioritized over footprint and gate consistency.
AO3400	R_DS(on) = 0.042 Ω at V_GS = 10 V; same TSOP-6; Q_g = 17 nC (higher); no halogen-free certification.	Higher gate charge increases driver loss; lacks IEC 61249-2-21 compliance required for some OEM programs.	Acceptable for cost-sensitive industrial designs where halogen-free and precise Q_g are not mandated.

Compared with DMN3026LSD-13 and AO3400, the SI3454CDV-T1-E3 offers the optimal balance of TSOP-6 footprint, guaranteed gate resistance, halogen-free compliance, and low Q_g-making it preferred for high-reliability, space-constrained notebook and portable SSD power management.

Availability

SI3454CDV-T1-E3 is available at Aetrix Electronics and suitable for notebook PC load switching, USB-C PD input staging, and portable SSD power rail control requiring stable component supply, long-term lifecycle support, and RoHS/halogen-free compliance.

Supply support for SI3454CDV-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global leader in discrete semiconductors, specializing in power MOSFETs, diodes, and optoelectronics with emphasis on reliability, thermal performance, and application-specific optimization.

The Si3454CDV belongs to Vishay's TrenchFET® Gen III family, engineered specifically for high-efficiency, low-voltage load switching in portable computing and battery-powered systems where thermal density and logic-level drive are critical.

FAQ

What is the maximum continuous drain current for SI3454CDV-T1-E3 at 70 °C case temperature?

The SI3454CDV-T1-E3 supports a continuous drain current of 3.3 A at T_C = 70 °C, as specified in the Absolute Maximum Ratings table. This derating reflects thermal limitations of the TSOP-6 package under sustained power dissipation; actual usable current depends on PCB copper area and ambient conditions. The SI3454CDV-T1-E3 maintains R_DS(on) stability across this range due to its trench architecture and −55 °C to +150 °C operating junction range.

Is SI3454CDV-T1-E3 suitable for 3.3 V logic-level gate drive?

Yes, the SI3454CDV-T1-E3 has a gate threshold voltage V_GS(th) of 1–3 V and delivers R_DS(on) = 0.079 Ω at V_GS = 4.5 V and I_D = 3.1 A, confirming robust enhancement with 3.3 V microcontroller outputs. Its low V_GS(th) tolerance and 100% R_g testing ensure consistent turn-on behavior across voltage and temperature extremes-critical for reliable operation in SI3454CDV-T1-E3-based load switches.

Does SI3454CDV-T1-E3 include integrated ESD protection?

No, the SI3454CDV-T1-E3 does not feature integrated ESD protection circuitry. It relies on external layout practices and system-level TVS devices for HBM/CDM robustness. The datasheet specifies only gate-source leakage (±100 nA at ±20 V) and absolute maximum V_GS = ±20 V-indicating that transient overvoltage must be managed externally. Designers should implement appropriate PCB guard rings and input clamping when deploying SI3454CDV-T1-E3 in connector-facing positions.

What is the thermal resistance from junction to ambient for SI3454CDV-T1-E3 on a standard FR4 board?

The SI3454CDV-T1-E3 has a typical junction-to-ambient thermal resistance R_thJA of 80 °C/W when mounted on a 1" × 1" FR4 board, with a maximum of 100 °C/W. This value assumes standard JEDEC test conditions and defines the upper bound of power dissipation before exceeding T_J(max) = 150 °C. For improved thermal performance, the SI3454CDV-T1-E3's exposed drain pad should be connected to ≥1 cm² of inner-layer copper pour, reducing effective R_thJA by up to 30%.

Can SI3454CDV-T1-E3 be used in parallel configurations?

Yes, the SI3454CDV-T1-E3 can be paralleled for higher current capacity, provided gate drive impedance is matched and PCB layout ensures symmetrical current sharing. Its positive R_DS(on) temperature coefficient (confirmed by normalized R_DS(on) vs. T_J curves) promotes inherent current balancing. However, individual gate resistors (≥1 Ω) are recommended to damp oscillation, and thermal coupling between devices must be minimized. Each SI3454CDV-T1-E3 retains its own safe operating area limits.

SI3454CDV-T1-E3 Specifications

Product attributes: Attribute value

Manufacturer:: Vishay Siliconix

Series:: TrenchFET®

Package/Case:: SOT-23-6 Thin, TSOT-23-6

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 30 V

Current - Continuous Drain (Id) @ 25°C:: 4.2A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 4.5V, 10V

Rds On (Max) @ Id, Vgs:: 50mOhm @ 3.8A, 10V

Vgs(th) (Max) @ Id:: 3V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 10.6 nC @ 10 V

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: 305 pF @ 15 V

FET Feature:: -

Power Dissipation (Max):: 1.25W (Ta), 1.5W (Tc)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 6-TSOP

SI3454CDV-T1-E3 FAQ

1.How can I place an order for SI3454CDV-T1-E3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI3454CDV-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI3454CDV-T1-E3 reliable?

The price and inventory of SI3454CDV-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI3454CDV-T1-E3 is usually 5 days.

3.What payment methods are accepted for SI3454CDV-T1-E3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI3454CDV-T1-E3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI3454CDV-T1-E3?

SI3454CDV-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI3454CDV-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI3454CDV-T1-E3?

For technical support, including SI3454CDV-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI3454CDV-T1-E3 requirements.

6.How does Aetrix verify that SI3454CDV-T1-E3 is sourced from the original manufacturer or authorized distributors?

All SI3454CDV-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI3454CDV-T1-E3 meets industry standards.

7.What is the process for return or replacement of SI3454CDV-T1-E3?

All SI3454CDV-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SI3454CDV-T1-E3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI3454CDV-T1-E3 part is unused and in its original packaging.

Return procedure for SI3454CDV-T1-E3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …