Vishay Siliconix SI3469DV-T1-E3
- Part No.:
- SI3469DV-T1-E3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- SOT-23-6 Thin, TSOT-23-6
- Datasheet:
-
SI3469DV-T1-E3.pdf
- Description:
- MOSFET P-CH 20V 5A 6TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:7,067
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Product details
Overview
SI3469DV-T1-E3 from Vishay Siliconix is a P-channel 20-V TrenchFET® power MOSFET in TSOP-6 package, delivering RDS(on) = 0.030 Ω at VGS = −10 V and −6.7 A continuous drain current at TA = 25 °C, optimized for notebook PC and game machine load switching.
For engineers reviewing the SI3469DV-T1-E3 datasheet, SI3469DV-T1-E3 pinout, SI3469DV-T1-E3 application, or SI3469DV-T1-E3 equivalent, this device requires attention to gate threshold voltage (−1.0 to −3.0 V), thermal resistance (RthJA = 90 °C/W steady-state), body diode forward voltage (−0.8 to −1.2 V), and total gate charge (20–30 nC) for accurate load-switch timing and thermal design.
Technical Context
This MOSFET uses trench-gate silicon technology to achieve low on-resistance with fast switching characteristics. Its negative gate threshold enables direct logic-level control from 3.3 V or 5 V microcontrollers without level-shifting circuitry.
The TSOP-6 package integrates four parallel drain terminals (pins 1, 2, 5, 6) for enhanced current handling and thermal conduction to PCB copper, while gate (pin 3) and source (pin 4) are isolated for clean drive and return paths-critical for minimizing shoot-through risk in high-side switch configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | −20 V: Maximum reverse-blocking capability for 12 V rail switching with margin. |
| RDS(on) | 0.030 Ω @ VGS = −10 V: Enables <100 mW conduction loss at 6 A, reducing thermal load. |
| ID (continuous) | −6.7 A @ TA = 25 °C: Supports typical notebook peripheral load currents without forced cooling. |
| VGS(th) | −1.0 to −3.0 V: Ensures reliable turn-on with standard 3.3 V GPIO, avoiding marginal biasing. |
| Qg | 20–30 nC: Determines gate drive energy and switching speed; compatible with low-power drivers. |
| VSD | −0.8 to −1.2 V: Defines reverse recovery behavior during inductive load commutation. |
| RthJA | 90 °C/W (steady-state): Requires ≥1 in² of 2-oz copper pour for safe operation at full current. |
Pinout & Package
TSOP-6 surface-mount package with exposed drain paddle (pins 1, 2, 5, 6 tied internally); 3.05 mm × 2.85 mm footprint, 1.0 mm max height, JEDEC MO-193C compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 5, 6 | Drain (D) | Four parallel terminals forming primary current path and main thermal conduction path to PCB copper. |
| 3 | Gate (G) | Control input requiring ≤30 nC charge; sensitive to ESD; must be driven with low-impedance source. |
| 4 | Source (S) | Return node for load current; referenced to system ground in high-side switch configuration. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® architecture | Delivers 30% lower RDS(on) vs. planar P-channel MOSFETs at same voltage rating, improving efficiency in space-constrained loads. |
| Lead (Pb)-free and RoHS-compliant | Meets EU Directive 2002/95/EC; suitable for consumer electronics manufacturing with no lead exemption required. |
| Halogen-free construction | Complies with IEC 61249-2-21, reducing toxic gas emission during board rework or fire scenarios. |
| Low Qgd/Qgs ratio | 4.8 nC / 3.8 nC ≈ 1.26: Minimizes Miller-induced switching instability during hard commutation. |
Applications
| Notebook PC Load Switch | Game Machine Power Sequencing |
|---|---|
Use Scenario: Enabling/disabling USB-C port power delivery or discrete GPU VRM rails under OS control. IC Role / Device Role / Timing Role: High-side load switch controlled by embedded controller GPIO with <20 µs turn-on delay. Use Value: Prevents backfeed between powered and unpowered subsystems; eliminates need for external Schottky blocking diodes. | Use Scenario: Sequencing 5 V and 3.3 V rails for FPGA configuration and memory initialization in handheld gaming consoles. IC Role / Device Role / Timing Role: Controlled power gate with soft-start via RC gate resistor to limit inrush current. Use Value: Reduces peak inrush to <1.5 A, preventing brownout on shared 5 V supply during cold boot. |
| Desktop Motherboard Standby Control | Industrial Human-Machine Interface (HMI) Panel |
Use Scenario: Isolating always-on +5 VSB rail from USB peripherals during S4/S5 sleep states. IC Role / Device Role / Timing Role: Low-leakage (IDSS ≤ −1 µA) high-side switch enabling <10 µA system standby current. Use Value: Meets ACPI S5 power budget requirements without auxiliary LDO or leakage compensation circuitry. | Use Scenario: Controlling backlight LED driver enable in factory-floor HMIs exposed to wide ambient temperature swings. IC Role / Device Role / Timing Role: Robust load switch rated for −55 to +150 °C junction operation with stable RDS(on) up to 125 °C. Use Value: Eliminates thermal derating calculations across −40 to +85 °C operating range; maintains <0.055 Ω RDS(on) at 85 °C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar P-channel load switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI3467DV-T1-E3 | RDS(on) = 0.022 Ω @ −10 V, but lower ID = −5.0 A; smaller die size. | Better efficiency at <5 A, but less margin for transient surges. | Select when board space is tighter and peak load stays below 4.5 A. |
| DMN2011UFD-7 | Same VDS (−20 V), but RDS(on) = 0.035 Ω @ −4.5 V; higher Qg (36 nC). | Slower switching, higher gate drive demand; wider SO-8 footprint. | Choose only if existing layout uses SO-8 and thermal margin exceeds 15 °C. |
Compared with SI3469DV-T1-E3, SI3467DV-T1-E3 offers lower conduction loss at light loads but reduced surge tolerance, while DMN2011UFD-7 trades switching speed and package compatibility for broader distributor availability-neither is pin-compatible, requiring layout revision.
Availability
SI3469DV-T1-E3 is available at Aetrix Electronics and suitable for notebook PC, game machine, and desktop motherboard designs requiring stable component supply, Pb-free compliance, and verified thermal performance in TSOP-6 footprint.
Supply support for SI3469DV-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete power devices, precision resistors, and optoelectronics, with emphasis on reliability and thermal performance.
The Si3469DV product line targets high-efficiency, space-constrained load switching in portable computing and consumer electronics, leveraging TrenchFET® technology to maximize power density in small-outline packages.
FAQ
What is the maximum continuous drain current for SI3469DV-T1-E3 at 70 °C ambient?
The SI3469DV-T1-E3 supports −5.3 A continuous drain current at TA = 70 °C with proper PCB copper area. This value assumes mounting on a 1" × 1" FR4 board per datasheet note (a), and reflects thermal derating due to increased junction-to-ambient resistance at elevated ambient temperatures. Always verify actual board layout thermal performance before final design sign-off for SI3469DV-T1-E3.
Can SI3469DV-T1-E3 be driven directly from a 3.3 V microcontroller GPIO?
Yes, SI3469DV-T1-E3 has a gate threshold voltage range of −1.0 V to −3.0 V, ensuring reliable turn-on with 3.3 V logic (VGS = −3.3 V). However, RDS(on) will be higher at −4.5 V (0.051 Ω) than at −10 V (0.030 Ω), so conduction loss increases ~70%-acceptable for intermittent loads but should be evaluated for continuous operation in SI3469DV-T1-E3 designs.
What is the safe operating area (SOA) limitation for SI3469DV-T1-E3 in single-pulse conditions?
The SI3469DV-T1-E3 SOA curve shows it can sustain 10 A at −10 V for 10 ms in single-pulse mode, limited by RDS(on) heating. At higher voltages, current must be reduced-e.g., 2 A at −20 V-to stay within the DC boundary. These limits assume TJ ≤ 150 °C and proper PCB thermal design; transient SOA must be validated using the normalized thermal impedance curves in the SI3469DV-T1-E3 datasheet.
Does SI3469DV-T1-E3 include an integrated body diode, and what is its forward voltage?
Yes, SI3469DV-T1-E3 includes an inherent parasitic body diode with VSD = −0.8 to −1.2 V at IS = −1.7 A and VGS = 0 V. This diode conducts during reverse-current events (e.g., inductive load flyback) and must be considered in layout-especially for synchronous rectification or bidirectional current paths. Its recovery time (trr = 25–50 ns) is documented in the SI3469DV-T1-E3 datasheet under dynamic parameters.
How does the TSOP-6 package of SI3469DV-T1-E3 improve thermal performance over standard SO-8?
The TSOP-6 package of SI3469DV-T1-E3 reduces thermal resistance to ambient (RthJA = 90 °C/W) versus typical SO-8 (≈120–150 °C/W) by integrating four drain pins as a unified thermal plane. This allows more efficient heat spreading into PCB copper, especially when using the recommended "T-shaped" copper pour footprint. The result is up to 25 °C lower junction temperature under identical load conditions compared to SO-8 alternatives like SI3469DV-T1-E3's larger-footprint counterparts.
SI3469DV-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- SOT-23-6 Thin, TSOT-23-6
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 5A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 30mOhm @ 6.7A, 10V
- Vgs(th) (Max) @ Id:
- 3V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 30 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- -
- FET Feature:
- -
- Power Dissipation (Max):
- 1.14W (Ta)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSOP
SI3469DV-T1-E3 FAQ
1.How can I place an order for SI3469DV-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI3469DV-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI3469DV-T1-E3 reliable?
The price and inventory of SI3469DV-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI3469DV-T1-E3 is usually 5 days.
3.What payment methods are accepted for SI3469DV-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI3469DV-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI3469DV-T1-E3?
SI3469DV-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI3469DV-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI3469DV-T1-E3?
For technical support, including SI3469DV-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI3469DV-T1-E3 requirements.
6.How does Aetrix verify that SI3469DV-T1-E3 is sourced from the original manufacturer or authorized distributors?
All SI3469DV-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI3469DV-T1-E3 meets industry standards.
7.What is the process for return or replacement of SI3469DV-T1-E3?
All SI3469DV-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SI3469DV-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI3469DV-T1-E3 part is unused and in its original packaging.
Return procedure for SI3469DV-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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