Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Vishay Siliconix SI5406CDC-T1-GE3

Name: SI5406CDC-T1-GE3
Brand: Vishay Siliconix
SKU: SI5406CDC-T1-GE3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5406CDC-T1-GE3

Manufacturer:: Vishay Siliconix

Category:: FETs, MOSFETs

Package:: 8-SMD, Flat Leads

Datasheet:: SI5406CDC-T1-GE3.pdf

Description:: MOSFET N-CH 12V 6A 1206-8

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:6,161

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5406CDC-T1-GE3 from Vishay Siliconix is an N-channel 12-V (D-S) TrenchFET® Power MOSFET in a leadless 1206-8 ChipFET® package, delivering R_DS(on) = 0.020 Ω at V_GS = 4.5 V, 6 A continuous drain current, and 11.5 nC total gate charge - optimized for load switching in space-constrained battery-powered mobile devices.

For engineers reviewing the SI5406CDC-T1-GE3 datasheet, SI5406CDC-T1-GE3 pinout, SI5406CDC-T1-GE3 application, or SI5406CDC-T1-GE3 equivalent, key selection criteria include its low-voltage gate drive compatibility (1.8 V–4.5 V), halogen-free/lead-free construction, thermal performance via drain-connected foot, and suitability for high-density portable power switching where board area and thermal resistance are critical.

Technical Context

This device employs trench-based silicon process technology to achieve low on-resistance with fast switching characteristics: t_d(on) = 10–20 ns, t_f = 20–30 ns, and Q_gd = 2 nC at V_DS = 6 V, enabling efficient operation in high-frequency DC-DC and load-switching topologies. Its gate threshold voltage (V_GS(th) = 0.4–1.0 V) ensures reliable turn-on with logic-level drivers.

The 1206-8 ChipFET® package integrates eight terminals - seven drain pads and one source pad - with a single gate terminal, leveraging short internal leads and exposed copper drain foot to achieve R_thJF = 18–22 °C/W (steady-state) and R_thJA = 45–55 °C/W (on 1" × 1" FR4), matching SO-8 thermal capability in 20% of the footprint.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	12 V - supports input rails up to 12 V without breakdown; suitable for Li-ion battery systems and USB-powered circuits.
R_DS(on) @ V_GS = 4.5 V	0.020 Ω - enables ≤120 mW conduction loss at 6 A, reducing heat generation in compact layouts.
I_D (continuous)	6 A - package-limited current rating at T_C = 25 °C; sufficient for PA bias switching and main power rail control.
Q_g (total)	11.5 nC - low gate charge minimizes driver power and enables fast switching with standard logic-level GPIOs.
V_GS(th)	0.4–1.0 V - ensures robust turn-on with 1.8 V and higher I/O supplies; avoids marginal gate drive in low-voltage systems.
R_thJF	18–22 °C/W - junction-to-foot thermal resistance confirms efficient heat transfer directly into PCB copper through exposed drain terminals.
Body diode V_SD	0.8–1.2 V - forward voltage at I_S = 6.9 A; supports synchronous rectification and reverse-current blocking in bidirectional paths.

Pinout & Package

The SI5406CDC-T1-GE3 uses the 1206-8 ChipFET® package: leadless, surface-mount, 2.95–3.10 mm × 1.825–1.975 mm footprint, with exposed copper drain terminals on the bottom side. Thermal performance relies on soldering all drain pads to adequate PCB copper area.

Pin/Terminal	Circuit Role	Design Meaning
1,2,3,6,7,8 (Drain)	Drain connection (x6)	Multiple parallel drain terminals reduce effective R_DS(on) and lower thermal resistance to PCB; must be connected to thermal copper pour.
4 (Gate)	Control input	Single gate terminal accepts logic-level drive; low C_iss = 1100 pF and R_g = 2.2 Ω support clean edge rates with minimal external gate resistance.
5 (Source)	Reference node / return path	Single-source terminal establishes common reference for gate drive and load current return; connects to system ground plane.

Key Features

Feature	Design Value
TrenchFET® technology	Enables 12 V V_DS rating with ultra-low R_DS(on) at 1.8 V gate drive - critical for modern low-power mobile SoC interfaces.
1206-8 ChipFET® package	Same footprint as 1206 passives but delivers SO-8-level power handling in 20% board area - ideal for ultra-thin smartphones and wearables.
Halogen-free & Pb-free	Meets RoHS Directive 2011/65/EU and JEDEC J-STD-020 moisture sensitivity level 1 - supports automated reflow without special handling.
Low Q_gd/Q_g ratio	Q_gd = 2 nC / Q_g = 11.5 nC ≈ 17% - improves hard-switching efficiency and reduces Miller-induced shoot-through risk in H-bridge configurations.
Body diode t_rr	25–40 ns - fast recovery enables use in synchronous buck converters and reverse-polarity protection without external Schottky.

Applications

Cellular PA Switching	Battery Load Switching
Use Scenario: Switching RF power amplifier bias voltage in 4G/5G handsets during transmit/receive mode transitions. IC Role / Device Role / Timing Role: High-speed load switch controlling V_PA rail; operates with <20 ns turn-off delay to minimize TX/RX overlap. Use Value: Low R_DS(on) and fast t_d(off) = 45–70 ns reduce insertion loss and enable precise timing control in envelope-tracking architectures.	Use Scenario: Enabling/disabling main system power from single-cell Li-ion (2.8–4.2 V) to processor or display subsystems. IC Role / Device Role / Timing Role: Primary power rail switch; driven by PMIC or baseband processor GPIO with 1.8 V logic compatibility. Use Value: V_GS(th) = 0.4–1.0 V ensures full enhancement at battery minimum; R_DS(on) = 0.027 Ω @ 1.8 V limits dropout to <100 mV at 3.7 A.
USB OTG Power Control	Smartphone Camera Flash Driver
Use Scenario: Controlling VBUS power delivery from smartphone to peripheral during USB On-The-Go operation. IC Role / Device Role / Timing Role: Reverse-current protected load switch placed between battery and USB port; body diode blocks backfeed. Use Value: Integrated body diode with V_SD = 0.8–1.2 V and t_rr = 25–40 ns eliminates need for discrete diode, saving space and BOM cost.	Use Scenario: Driving high-current LED flash arrays requiring pulsed 2–3 A currents with tight timing control. IC Role / Device Role / Timing Role: Fast-switching current sink; gate driven by camera ISP PWM output with minimal external components. Use Value: Low Q_g = 11.5 nC allows clean 100 kHz+ PWM edges; R_DS(on) = 0.023 Ω @ 2.5 V ensures >90% efficiency at 2.5 A peak.

Cellular PA Switching

Battery Load Switching

Use Scenario: Switching RF power amplifier bias voltage in 4G/5G handsets during transmit/receive mode transitions.

IC Role / Device Role / Timing Role: High-speed load switch controlling V_PA rail; operates with <20 ns turn-off delay to minimize TX/RX overlap.

Use Value: Low R_DS(on) and fast t_d(off) = 45–70 ns reduce insertion loss and enable precise timing control in envelope-tracking architectures.

Use Scenario: Enabling/disabling main system power from single-cell Li-ion (2.8–4.2 V) to processor or display subsystems.

IC Role / Device Role / Timing Role: Primary power rail switch; driven by PMIC or baseband processor GPIO with 1.8 V logic compatibility.

Use Value: V_GS(th) = 0.4–1.0 V ensures full enhancement at battery minimum; R_DS(on) = 0.027 Ω @ 1.8 V limits dropout to <100 mV at 3.7 A.

USB OTG Power Control

Smartphone Camera Flash Driver

Use Scenario: Controlling VBUS power delivery from smartphone to peripheral during USB On-The-Go operation.

IC Role / Device Role / Timing Role: Reverse-current protected load switch placed between battery and USB port; body diode blocks backfeed.

Use Value: Integrated body diode with V_SD = 0.8–1.2 V and t_rr = 25–40 ns eliminates need for discrete diode, saving space and BOM cost.

Use Scenario: Driving high-current LED flash arrays requiring pulsed 2–3 A currents with tight timing control.

IC Role / Device Role / Timing Role: Fast-switching current sink; gate driven by camera ISP PWM output with minimal external components.

Use Value: Low Q_g = 11.5 nC allows clean 100 kHz+ PWM edges; R_DS(on) = 0.023 Ω @ 2.5 V ensures >90% efficiency at 2.5 A peak.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel load switching applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5404DC-T1-GE3	R_DS(on) = 0.032 Ω @ 4.5 V; same 1206-8 package and V_DS = 12 V rating.	Higher on-resistance increases conduction loss by ~60% at 6 A; acceptable where thermal margin exists and cost is prioritized.	Select when lower gate charge (Q_g = 7.5 nC) and reduced driver loading outweigh R_DS(on) penalty.
DMN10H015LQ-7	R_DS(on) = 0.015 Ω @ 4.5 V; 1206-8 package; V_DS = 10 V (not 12 V).	Lower R_DS(on) improves efficiency but 10 V V_DS rating excludes use in 12 V systems or transient-tolerant designs.	Choose only if system maximum V_DS stress remains ≤9.5 V; verify transient immunity before substitution.

Compared with SI5406CDC-T1-GE3, Si5404DC-T1-GE3 trades higher conduction loss for lower gate drive demand, while DMN10H015LQ-7 offers superior R_DS(on) at the cost of reduced voltage margin - making SI5406CDC-T1-GE3 the balanced choice for 12 V-rated, space-constrained mobile power switching.

Availability

SI5406CDC-T1-GE3 is available at Aetrix Electronics and suitable for cellular PA switching, battery load management, and USB OTG power control requiring stable component supply, consistent lead-free compliance, and verified thermal performance in high-volume portable electronics manufacturing.

Supply support for SI5406CDC-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability power MOSFETs, diodes, and optoelectronics for demanding industrial and consumer applications.

The SI5406CDC-T1-GE3 belongs to Vishay's TrenchFET® ChipFET® family - engineered specifically for ultra-compact, high-efficiency load switching in battery-powered mobile devices where thermal density and gate-drive simplicity are paramount.

FAQ

What is the maximum continuous drain current for SI5406CDC-T1-GE3 at 85 °C case temperature?

The SI5406CDC-T1-GE3 supports 6 A continuous drain current at T_C = 85 °C, as specified in the Absolute Maximum Ratings table. This rating is package-limited and assumes proper PCB copper layout per Vishay Application Note AN811 - insufficient thermal copper will reduce achievable current due to junction temperature rise.

Does SI5406CDC-T1-GE3 require a heatsink for 6 A operation?

No external heatsink is required for SI5406CDC-T1-GE3 at 6 A if mounted on a standard 1" × 1" double-sided FR4 PCB with ≥2 oz copper on both layers and full-soldered drain pads. Its R_thJA = 45–55 °C/W and R_thJF = 18–22 °C/W enable direct thermal coupling to the PCB, eliminating need for mechanical heatsinks in handheld form factors.

Can SI5406CDC-T1-GE3 be driven directly by a 1.8 V GPIO?

Yes - SI5406CDC-T1-GE3 has V_GS(th) = 0.4–1.0 V and R_DS(on) = 0.027 Ω at V_GS = 1.8 V, ensuring full enhancement and low conduction loss with 1.8 V logic. Gate capacitance (C_iss = 1100 pF) is manageable for typical MCU GPIOs driving at ≤1 MHz.

What is the safe operating area (SOA) limitation for SI5406CDC-T1-GE3 at DC conditions?

At DC, the SI5406CDC-T1-GE3 SOA is limited by R_DS(on) and package thermal resistance. For example, at V_DS = 6 V and T_J = 150 °C, maximum sustainable I_D ≈ 3.3 A (based on P_D = (T_J − T_A) / R_thJA). The datasheet Figure 6 provides full SOA curves including pulse limits.

Is SI5406CDC-T1-GE3 suitable for reverse polarity protection?

Yes - SI5406CDC-T1-GE3 can implement reverse polarity protection by orienting source to input and drain to load. Its body diode blocks reverse current, and R_DS(on) = 0.020 Ω at 4.5 V ensures low forward drop. However, external gate control is required to disable conduction during fault conditions.

SI5406CDC-T1-GE3 Specifications

Product attributes: Attribute value

Manufacturer:: Vishay Siliconix

Series:: TrenchFET®

Package/Case:: 8-SMD, Flat Leads

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 12 V

Current - Continuous Drain (Id) @ 25°C:: 6A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 1.8V, 4.5V

Rds On (Max) @ Id, Vgs:: 20mOhm @ 6.5A, 4.5V

Vgs(th) (Max) @ Id:: 1V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 32 nC @ 8 V

Vgs (Max):: ±8V

Input Capacitance (Ciss) (Max) @ Vds:: 1100 pF @ 6 V

FET Feature:: -

Power Dissipation (Max):: 2.3W (Ta), 5.7W (Tc)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 1206-8 ChipFET™

SI5406CDC-T1-GE3 FAQ

1.How can I place an order for SI5406CDC-T1-GE3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5406CDC-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5406CDC-T1-GE3 reliable?

The price and inventory of SI5406CDC-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5406CDC-T1-GE3 is usually 5 days.

3.What payment methods are accepted for SI5406CDC-T1-GE3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5406CDC-T1-GE3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5406CDC-T1-GE3?

SI5406CDC-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5406CDC-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5406CDC-T1-GE3?

For technical support, including SI5406CDC-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5406CDC-T1-GE3 requirements.

6.How does Aetrix verify that SI5406CDC-T1-GE3 is sourced from the original manufacturer or authorized distributors?

All SI5406CDC-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5406CDC-T1-GE3 meets industry standards.

7.What is the process for return or replacement of SI5406CDC-T1-GE3?

All SI5406CDC-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SI5406CDC-T1-GE3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5406CDC-T1-GE3 part is unused and in its original packaging.

Return procedure for SI5406CDC-T1-GE3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …