Vishay Siliconix SI5853CDC-T1-E3
- Part No.:
- SI5853CDC-T1-E3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- 8-SMD, Flat Leads
- Datasheet:
-
SI5853CDC-T1-E3.pdf
- Description:
- MOSFET P-CH 20V 4A 1206-8
- Quantity:
- Payment:

- Shipping:

Inventory:4,448
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5853CDC-T1-E3 from Vishay Siliconix is a P-channel 20 V (D-S) MOSFET with integrated trench Schottky diode in a 1206-8 ChipFET package. It delivers RDS(on) = 0.104 Ω at VGS = −4.5 V, supports −4 A continuous drain current (TC = 25 °C), and features 0.46 V forward voltage at 0.5 A for the Schottky element - optimized for portable device charging switches requiring low-loss reverse polarity protection and fast switching.
For engineers reviewing the SI5853CDC-T1-E3 datasheet, SI5853CDC-T1-E3 pinout, SI5853CDC-T1-E3 application, or SI5853CDC-T1-E3 equivalent, key selection criteria include verified P-channel logic-level gate drive compatibility, integrated Schottky VF and IF ratings, thermal resistance to ambient (RthJA = 70 °C/W typical), and ChipFET package footprint constraints for space-constrained battery-powered designs.
Technical Context
This device integrates a P-channel Trench MOSFET and a monolithically co-packaged low-VF Schottky diode sharing common Drain and Source terminals. Its gate threshold voltage (VGS(th) = −0.45 to −1.0 V) enables direct interface with 1.8 V/2.5 V/3.3 V logic controllers without level shifting. The Schottky junction exhibits 0.381 V typical forward drop at 0.5 A and <32 mA reverse leakage at 20 V and 125 °C.
The MOSFET operates with total gate charge Qg = 4.2 nC (at VGS = −4.5 V), enabling efficient switching in high-frequency load-switching applications. Thermal design is constrained by RthJF = 33 °C/W (MOSFET) and RthJF = 40 °C/W (Schottky), with both elements sharing the same die substrate and thermal path to the exposed drain pad.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | −20 V maximum - defines safe blocking capability for USB OTG, power bank, and single-cell Li-ion systems. |
| RDS(on) | 0.104 Ω at VGS = −4.5 V - determines conduction loss of ≤ 1.04 W at −3.2 A, critical for thermal management in sealed enclosures. |
| ID (cont.) | −4 A at TC = 25 °C - sets maximum steady-state load current before derating due to package thermal limits. |
| VF (Schottky) | 0.46 V at IF = 0.5 A - minimizes forward conduction loss during reverse-current protection or diode-OR operation. |
| Qg | 4.2 nC at VGS = −4.5 V - governs required gate driver current and switching transition time in PWM-controlled power paths. |
| RthJA | 70 °C/W typical - establishes worst-case junction temperature rise under natural convection on FR4 PCB, guiding heatsinking decisions. |
| VGS(th) | −0.45 to −1.0 V - ensures reliable turn-on with standard logic-level outputs, eliminating need for external gate bias circuitry. |
Pinout & Package
SI5853CDC-T1-E3 uses the surface-mount 1206-8 ChipFET package with an exposed drain pad for thermal and electrical connection. The package has no leads; terminals are soldered directly to copper pads on the PCB. Pin 1 (Gate) and Pin 2 (Source) are on the top side; Drain is the bottom-side exposed metal pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate | Controls MOSFET channel conduction; requires ≥1.8 V negative swing relative to Source to fully enhance. |
| 2 (S) | Source | Common reference node for gate drive and Schottky cathode; connects to system ground or battery negative in high-side switch configurations. |
| Drain (exposed pad) | Drain / Schottky Anode | Shared terminal for MOSFET drain and Schottky anode; must be soldered to large copper pour for thermal dissipation and low-inductance current return path. |
Key Features
| Feature | Design Value |
|---|---|
| LITTLE FOOT® Plus integration | Monolithic co-packaging of P-MOSFET + Schottky eliminates discrete layout area and parasitic inductance between devices. |
| Trench Schottky diode | 0.46 V VF at 0.5 A enables >95 % efficiency in reverse-polarity protection circuits at low currents. |
| Logic-level gate drive | VGS(th) down to −0.45 V allows direct control from microcontroller GPIOs without external level shifters or charge pumps. |
| Halogen-free & RoHS-compliant | Meets IEC 61249-2-21 and Directive 2002/95/EC - supports environmental compliance for consumer electronics exports. |
| ChipFET thermal performance | RthJF = 33 °C/W (MOSFET) enables 2.5 W dissipation with <85 °C junction rise above case - suitable for unheatsinked portable designs. |
Applications
| USB Power Delivery Switching | Li-ion Battery Protection |
|---|---|
Use Scenario: Bidirectional power routing in dual-role USB-C ports where host/peripheral roles dynamically switch. IC Role / Device Role / Timing Role: P-channel MOSFET acts as high-side load switch; integrated Schottky prevents backfeed during role swap and clamps inductive transients. Use Value: Eliminates need for separate TVS and reverse-blocking diode, reducing BOM count by two components while maintaining <100 ns transient response. | Use Scenario: Reverse-current blocking in single-cell Li-ion battery packs during charging and standby. IC Role / Device Role / Timing Role: Functions as ideal diode replacement in battery protection FET stack, with Schottky providing fast freewheeling path during overcurrent shutdown. Use Value: 0.46 V VF reduces standby power loss by 60 % vs. standard silicon diodes, extending shelf life in low-power IoT sensors. |
| Portable Device Charging Switch | Power Bank Output Regulation |
Use Scenario: Controlled enable/disable of charging path from wall adapter to internal battery in smartphones and tablets. IC Role / Device Role / Timing Role: High-side P-MOSFET provides ON/OFF control; Schottky conducts reverse leakage during adapter removal to prevent voltage droop. Use Value: RDS(on) = 0.104 Ω limits conduction loss to <1.1 W at 3.2 A, enabling compact thermal design without active cooling. | Use Scenario: Output stage of multi-cell power banks delivering regulated 5 V/9 V/12 V to USB-C devices. IC Role / Device Role / Timing Role: Acts as output OR-ing switch, selecting between battery and boost converter paths while preventing backflow. Use Value: Integrated Schottky's 1 A average forward rating supports sustained 5 V/3 A output without external diode, simplifying layout and improving EMI performance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar P-channel MOSFET-with-integrated-Schottky applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5851CDC-T1-E3 | RDS(on) = 0.144 Ω at VGS = −2.5 V; identical package and Schottky specs. | Higher gate threshold sensitivity - better suited for 2.5 V logic control but less margin at 1.8 V. | Select when gate drive voltage is limited to 2.5 V and lower switching speed is acceptable. |
| DMN2011LSD-13 | P-channel only (no integrated Schottky); RDS(on) = 0.115 Ω at VGS = −4.5 V; same 1206-8 footprint. | Requires external Schottky for reverse protection - adds 0.5 mm² board area and 0.3 nH parasitic inductance. | Choose when Schottky function is implemented elsewhere or when higher reliability via discrete diode selection is prioritized. |
Compared with SI5853CDC-T1-E3, Si5851CDC-T1-E3 trades lower gate drive voltage compatibility for slightly higher RDS(on), while DMN2011LSD-13 offers identical MOSFET performance but shifts Schottky integration responsibility to the system designer - impacting layout density, EMI, and component count.
Availability
SI5853CDC-T1-E3 is available at Aetrix Electronics and suitable for portable device charging switches, USB-C power delivery routing, and Li-ion battery protection circuits requiring stable component supply, lead-free compliance, and validated thermal performance in ChipFET packages.
Supply support for SI5853CDC-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in MOSFETs, diodes, and optoelectronics with emphasis on power efficiency and miniaturization.
The Si585x CDC family targets space-constrained portable power management, integrating trench MOSFETs and Schottky diodes to replace dual-component solutions in battery-connected systems.
FAQ
What is the maximum continuous drain current rating for SI5853CDC-T1-E3 at 70 °C case temperature?
The SI5853CDC-T1-E3 supports −3.4 A continuous drain current at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This derating reflects thermal limitations of the 1206-8 ChipFET package under sustained power dissipation; operation above this current requires forced airflow or enhanced PCB copper area to maintain junction temperature below 150 °C.
Does SI5853CDC-T1-E3 require a gate resistor for stable switching in a 1 MHz load-switch application?
SI5853CDC-T1-E3 does not mandate an external gate resistor for stability, but a 1–10 Ω series resistor is recommended to dampen ringing caused by gate loop inductance and reduce EMI. With Qg = 4.2 nC and typical gate resistance Rg = 6.2 Ω, the device achieves 15–25 ns turn-on delay at VGEN = −4.5 V, making it suitable for 1 MHz operation when paired with a low-impedance driver.
Can SI5853CDC-T1-E3 be used in a high-side configuration with 1.8 V logic-level control?
Yes, SI5853CDC-T1-E3 can be used in high-side configuration with 1.8 V logic-level control because its VGS(th) minimum is −0.45 V, ensuring full enhancement at VGS = −1.8 V. However, RDS(on) increases to 0.205 Ω at VGS = −1.8 V, so conduction loss must be evaluated at the target load current - e.g., 1.33 W at −2.5 A.
What is the Schottky diode's reverse leakage current specification for SI5853CDC-T1-E3 at 20 V and 125 °C?
The SI5853CDC-T1-E3 Schottky diode exhibits a maximum reverse leakage current of 32 mA at VR = 20 V and TJ = 125 °C, per the Schottky Specifications table. This value is critical for standby power budgeting in always-on battery systems, where even milliamp-level leakage impacts shelf life over months of storage.
Is the exposed drain pad of SI5853CDC-T1-E3 electrically isolated from other terminals?
No, the exposed drain pad of SI5853CDC-T1-E3 is not electrically isolated - it is the MOSFET's Drain terminal and also serves as the Schottky diode's Anode. It must be connected to the same net as the top-side Drain pin (shared internally) and should be soldered to a dedicated copper pour tied to the system's high-side power rail or ground return, depending on circuit topology.
SI5853CDC-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- LITTLE FOOT®
- Package/Case:
- 8-SMD, Flat Leads
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- P-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 4A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 1.8V, 4.5V
- Rds On (Max) @ Id, Vgs:
- 104mOhm @ 2.5A, 4.5V
- Vgs(th) (Max) @ Id:
- 1V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 11 nC @ 8 V
- Vgs (Max):
- ±8V
- Input Capacitance (Ciss) (Max) @ Vds:
- 350 pF @ 10 V
- FET Feature:
- Schottky Diode (Isolated)
- Power Dissipation (Max):
- 1.5W (Ta), 3.1W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 1206-8 ChipFET™
SI5853CDC-T1-E3 FAQ
1.How can I place an order for SI5853CDC-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5853CDC-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5853CDC-T1-E3 reliable?
The price and inventory of SI5853CDC-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5853CDC-T1-E3 is usually 5 days.
3.What payment methods are accepted for SI5853CDC-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5853CDC-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5853CDC-T1-E3?
SI5853CDC-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5853CDC-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5853CDC-T1-E3?
For technical support, including SI5853CDC-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5853CDC-T1-E3 requirements.
6.How does Aetrix verify that SI5853CDC-T1-E3 is sourced from the original manufacturer or authorized distributors?
All SI5853CDC-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5853CDC-T1-E3 meets industry standards.
7.What is the process for return or replacement of SI5853CDC-T1-E3?
All SI5853CDC-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SI5853CDC-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5853CDC-T1-E3 part is unused and in its original packaging.
Return procedure for SI5853CDC-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5853CDC-T1-E3 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

