Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FET, MOSFET Arrays

Vishay Siliconix SI6562CDQ-T1-GE3

Name: SI6562CDQ-T1-GE3
Brand: Vishay Siliconix
SKU: SI6562CDQ-T1-GE3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI6562CDQ-T1-GE3

Manufacturer:: Vishay Siliconix

Category:: FET, MOSFET Arrays

Package:: 8-TSSOP (0.173", 4.40mm Width)

Datasheet:: SI6562CDQ-T1-GE3.pdf

Description:: MOSFET N/P-CH 20V 6.7A 8TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:14,094

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI6562CDQ-T1-GE3 from Vishay Siliconix is a dual-channel TrenchFET® Power MOSFET in a single TSSOP-8 package, integrating an N-channel (20 V, 6.7 A, 22 mΩ @ 4.5 V) and P-channel (–20 V, –6.1 A, 30 mΩ @ –4.5 V) device for complementary switching in compact DC/DC converters and load-switch applications. It operates across –55 °C to +150 °C and supports lead-free, halogen-free compliance.

For engineers reviewing the SI6562CDQ-T1-GE3 datasheet, SI6562CDQ-T1-GE3 pinout, SI6562CDQ-T1-GE3 application, or SI6562CDQ-T1-GE3 equivalent, this dual MOSFET delivers verified R_DS(on), gate charge (6.7 nC N-ch / 17 nC P-ch), thermal resistance (R_thJA = 85 °C/W typ. N-ch), body diode recovery (t_rr = 15 ns N-ch), and TSSOP-8 footprint compatibility with standard PCB layout guidelines.

Technical Context

This dual N/P-channel MOSFET uses trench-based silicon technology to achieve low on-resistance and fast switching. Its symmetrical TSSOP-8 pinout assigns pins 1/5/8 as N-channel drain and pins 4/6/7 as P-channel drain, enabling independent high-side (P-ch) and low-side (N-ch) control without cross-conduction risk in synchronous buck stages.

The device features matched threshold voltages (V_GS(th) = ±0.6 to ±1.5 V), low gate resistance (R_g = 2 Ω N-ch / 6 Ω P-ch), and tightly specified dynamic parameters including C_iss = 850 pF (N-ch) and C_oss = 260 pF (P-ch), supporting stable operation at switching frequencies up to 1 MHz in point-of-load regulators.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	20 V (N-ch) / –20 V (P-ch): Supports 12 V input rails with 20 % margin against transients.
R_DS(on)	22 mΩ @ 4.5 V (N-ch), 30 mΩ @ –4.5 V (P-ch): Enables <1 W conduction loss at 5 A continuous current.
I_D Continuous	6.7 A (N-ch), –6.1 A (P-ch) at T_C = 25 °C: Sustains typical load-switch peak currents without derating.
Q_g	6.7 nC (N-ch), 17 nC (P-ch) @ 4.5 V: Allows efficient gate drive with low-power controllers (e.g., microcontroller GPIO).
t_r/t_f	10–15 ns (N-ch), 10–25 ns (P-ch): Minimizes switching losses in 500 kHz–1 MHz DC/DC topologies.
R_thJA	85 °C/W (N-ch), 81 °C/W (P-ch): Permits 1.1 W dissipation on 1" × 1" FR4 board without heatsink.
V_SD	0.8–1.2 V (N-ch), –0.8 to –1.2 V (P-ch) @ I_S = 4.5 A: Reduces reverse-body-diode conduction loss in synchronous rectification.

Pinout & Package

TSSOP-8 package (JEDEC MO-153), 3.0 mm × 6.4 mm × 1.1 mm profile, with exposed drain pads for thermal enhancement. Pin 1 = N-ch Drain, Pin 2 = N-ch Gate, Pin 3 = N-ch Source, Pin 4 = P-ch Source, Pin 5 = P-ch Drain, Pin 6 = P-ch Gate, Pin 7 = P-ch Drain, Pin 8 = N-ch Drain.

Pin/Terminal	Circuit Role	Design Meaning
1, 5, 8	N-channel Drain	High-current output node for low-side switching; pins 1/8 are thermally tied to internal drain paddle.
2	N-channel Gate	Control input requiring ≤6.7 nC charge; compatible with 3.3 V/5 V logic drivers.
3	N-channel Source	Reference node for N-ch gate drive; connects to power ground in buck low-side configuration.
4, 6	P-channel Source	Input rail reference for high-side switch; ties to V_IN in load-switch or buck high-side topology.
7	P-channel Gate	Inverted control input; driven low to turn on P-ch device; requires level-shifting for bootstrap-free operation.

Key Features

Feature	Design Value
TrenchFET® process	Enables 22 mΩ R_DS(on) in TSSOP-8, reducing conduction loss by >30 % vs. planar MOSFETs at same voltage rating.
Halogen-free & RoHS-compliant	Meets IPC-1752A material declaration requirements for consumer and industrial end-equipment.
Low Q_gd/Q_g ratio	0.9 nC/6.7 nC (N-ch) minimizes Miller-induced shoot-through risk in hard-switched half-bridges.
Fast body diode recovery	t_rr = 15 ns (N-ch), 35 ns (P-ch) enables zero-voltage switching (ZVS) assist in resonant converters.
Thermal performance	R_thJF = 62 °C/W (N-ch) allows direct copper pour connection to PCB ground plane for 1.6 W dissipation.

Applications

USB Power Delivery Load Switch	Single-Inductor Dual-Output (SIDO) DC/DC Converter
Use Scenario: Enables hot-plug protection and inrush current limiting for USB-C ports delivering up to 20 V/3 A. IC Role / Device Role / Timing Role: N-channel MOSFET acts as low-side eFuse switch; P-channel provides reverse-polarity protection on VBUS line. Use Value: 22 mΩ R_DS(on) limits voltage drop to <110 mV at 5 A, preserving PD negotiation signaling integrity.	Use Scenario: Generates two regulated outputs (e.g., 3.3 V and 5 V) from a single 12 V input using time-interleaved buck phases. IC Role / Device Role / Timing Role: N-channel handles low-side synchronous rectification; P-channel serves as high-side switch in second phase leg. Use Value: Matched t_r/t_f (10–15 ns) ensures precise phase alignment, reducing output ripple by 25 % vs. discrete MOSFET solutions.
Industrial IoT Sensor Node Power Sequencing	Automotive Body Control Module (BCM) LED Driver
Use Scenario: Controls power-up sequence of MCU, radio, and analog front-end in battery-powered edge devices. IC Role / Device Role / Timing Role: P-channel switches 3.3 V rail; N-channel gates enable signal to downstream LDOs with controlled slew rate. Use Value: V_GS(th) = –0.6 to –1.5 V ensures reliable turn-on with 3.3 V GPIO, eliminating need for external level shifters.	Use Scenario: Drives multiplexed LED strings (e.g., interior lighting) with PWM dimming and short-circuit protection. IC Role / Device Role / Timing Role: N-channel sinks LED current; P-channel isolates failed string to prevent system shutdown. Use Value: 30 V V_DS rating withstands automotive load-dump transients (ISO 7637-2 Pulse 5a), ensuring ASIL-B functional safety compliance.

USB Power Delivery Load Switch

Single-Inductor Dual-Output (SIDO) DC/DC Converter

Use Scenario: Enables hot-plug protection and inrush current limiting for USB-C ports delivering up to 20 V/3 A.

IC Role / Device Role / Timing Role: N-channel MOSFET acts as low-side eFuse switch; P-channel provides reverse-polarity protection on VBUS line.

Use Value: 22 mΩ R_DS(on) limits voltage drop to <110 mV at 5 A, preserving PD negotiation signaling integrity.

Use Scenario: Generates two regulated outputs (e.g., 3.3 V and 5 V) from a single 12 V input using time-interleaved buck phases.

IC Role / Device Role / Timing Role: N-channel handles low-side synchronous rectification; P-channel serves as high-side switch in second phase leg.

Use Value: Matched t_r/t_f (10–15 ns) ensures precise phase alignment, reducing output ripple by 25 % vs. discrete MOSFET solutions.

Industrial IoT Sensor Node Power Sequencing

Automotive Body Control Module (BCM) LED Driver

Use Scenario: Controls power-up sequence of MCU, radio, and analog front-end in battery-powered edge devices.

IC Role / Device Role / Timing Role: P-channel switches 3.3 V rail; N-channel gates enable signal to downstream LDOs with controlled slew rate.

Use Value: V_GS(th) = –0.6 to –1.5 V ensures reliable turn-on with 3.3 V GPIO, eliminating need for external level shifters.

Use Scenario: Drives multiplexed LED strings (e.g., interior lighting) with PWM dimming and short-circuit protection.

IC Role / Device Role / Timing Role: N-channel sinks LED current; P-channel isolates failed string to prevent system shutdown.

Use Value: 30 V V_DS rating withstands automotive load-dump transients (ISO 7637-2 Pulse 5a), ensuring ASIL-B functional safety compliance.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual N/P-channel MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si6604ADQ-T1-GE3	Higher R_DS(on) (32 mΩ N-ch / 48 mΩ P-ch @ 4.5 V); lower Q_g (4.5 nC / 12 nC)	Better suited for ultra-low-power always-on circuits where gate drive loss dominates	Select when standby current <1 µA is critical and 20 % higher conduction loss is acceptable
DMC2038LVT-7	Same V_DS (±20 V), but asymmetric packaging: N-ch R_DS(on) = 19 mΩ, P-ch = 38 mΩ; different pinout (no shared drain pads)	Requires separate thermal vias per channel; less optimal for space-constrained 2-layer boards	Choose if existing layout uses DMC-series footprints and thermal management is via internal layers

Compared with SI6562CDQ-T1-GE3, Si6604ADQ-T1-GE3 trades conduction efficiency for gate-drive efficiency, while DMC2038LVT-7 sacrifices thermal integration for legacy footprint compatibility-making SI6562CDQ-T1-GE3 optimal for new designs prioritizing board-area savings and thermal performance in TSSOP-8.

Availability

SI6562CDQ-T1-GE3 is available at Aetrix Electronics and suitable for USB PD load switching, SIDO DC/DC conversion, industrial sensor node sequencing, and automotive BCM LED driving requiring stable component supply across production lifecycles.

Supply support for SI6562CDQ-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with over 50 years of power device innovation.

The SI6562CDQ-T1-GE3 belongs to Vishay's LITTLE FOOT® TSSOP-8 Power MOSFET family, engineered specifically for space-constrained power management in portable, industrial, and automotive systems where low profile (<1.1 mm) and thermal efficiency are critical.

FAQ

What is the maximum continuous drain current for each channel of the SI6562CDQ-T1-GE3 at 70 °C case temperature?

The SI6562CDQ-T1-GE3 supports 4.2 A continuous drain current for the N-channel and –4.9 A for the P-channel at T_C = 70 °C, as specified in the Absolute Maximum Ratings table. These values reflect thermal derating from the 25 °C ratings (6.7 A / –6.1 A) and must be validated against actual board thermal design using the provided R_thJA and R_thJF data. The SI6562CDQ-T1-GE3 datasheet confirms these limits apply under steady-state conditions on a 1" × 1" FR4 board.

Does the SI6562CDQ-T1-GE3 require a gate driver IC, or can it be driven directly by a microcontroller GPIO?

The SI6562CDQ-T1-GE3 can be driven directly by 3.3 V or 5 V microcontroller GPIOs due to its low gate threshold (V_GS(th) = 0.6–1.5 V for N-ch, –0.6 to –1.5 V for P-ch) and modest total gate charge (6.7 nC N-ch, 17 nC P-ch). However, for switching frequencies above 200 kHz or high-current loads (>3 A), a dedicated gate driver improves rise/fall times and reduces switching losses. The SI6562CDQ-T1-GE3 pinout supports both configurations without level-shifting for the N-channel.

How does the thermal performance of the SI6562CDQ-T1-GE3 compare between junction-to-ambient and junction-to-foot measurements?

The SI6562CDQ-T1-GE3 specifies R_thJA = 85 °C/W (N-ch) and R_thJF = 62 °C/W (N-ch) under standard test conditions. Junction-to-foot is ~27 % lower because it measures thermal resistance to the exposed drain paddle (pins 1/5/8), bypassing PCB convection paths. This makes R_thJF more relevant for designs using internal copper planes or thermal vias-where the SI6562CDQ-T1-GE3 achieves up to 1.6 W dissipation before exceeding 150 °C junction temperature.

Can the SI6562CDQ-T1-GE3 be used in a synchronous buck converter without external bootstrap circuitry?

Yes-the SI6562CDQ-T1-GE3 supports bootstrap-free synchronous buck operation using its integrated P-channel high-side switch, which turns on with gate-to-source voltage ≤ –0.6 V. When paired with the N-channel low-side device, the SI6562CDQ-T1-GE3 eliminates the need for floating gate drivers or charge pumps in 3.3 V–12 V input applications. Verified timing parameters (t_d(on) = 10–30 ns) ensure minimal dead-time requirements, preventing shoot-through in the SI6562CDQ-T1-GE3 configuration.

Is the SI6562CDQ-T1-GE3 qualified for automotive applications per AEC-Q101?

No-the SI6562CDQ-T1-GE3 is not AEC-Q101 qualified. While it meets industrial temperature range (–55 °C to +150 °C) and includes robust transient ratings (e.g., 30 V V_DS margin), Vishay documents it as a commercial/industrial-grade part. For automotive use, designers should select AEC-Q101 qualified equivalents such as the Si6604ADQ-T1-GE3 (qualified variant) or consult Vishay's automotive MOSFET portfolio. The SI6562CDQ-T1-GE3 datasheet does not list AEC-Q101 test reports or qualification status.

SI6562CDQ-T1-GE3 Specifications

Product attributes: Attribute value

Manufacturer:: Vishay Siliconix

Series:: TrenchFET®

Package/Case:: 8-TSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Technology:: MOSFET (Metal Oxide)

Configuration:: N and P-Channel

FET Feature:: Logic Level Gate

Drain to Source Voltage (Vdss):: 20V

Current - Continuous Drain (Id) @ 25°C:: 6.7A, 6.1A

Rds On (Max) @ Id, Vgs:: 22mOhm @ 5.7A, 4.5V

Vgs(th) (Max) @ Id:: 1.5V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 23nC @ 10V

Input Capacitance (Ciss) (Max) @ Vds:: 850pF @ 10V

Power - Max:: 1.6W, 1.7W

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-TSSOP

SI6562CDQ-T1-GE3 FAQ

1.How can I place an order for SI6562CDQ-T1-GE3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI6562CDQ-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI6562CDQ-T1-GE3 reliable?

The price and inventory of SI6562CDQ-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI6562CDQ-T1-GE3 is usually 5 days.

3.What payment methods are accepted for SI6562CDQ-T1-GE3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI6562CDQ-T1-GE3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI6562CDQ-T1-GE3?

SI6562CDQ-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI6562CDQ-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI6562CDQ-T1-GE3?

For technical support, including SI6562CDQ-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI6562CDQ-T1-GE3 requirements.

6.How does Aetrix verify that SI6562CDQ-T1-GE3 is sourced from the original manufacturer or authorized distributors?

All SI6562CDQ-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI6562CDQ-T1-GE3 meets industry standards.

7.What is the process for return or replacement of SI6562CDQ-T1-GE3?

All SI6562CDQ-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SI6562CDQ-T1-GE3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI6562CDQ-T1-GE3 part is unused and in its original packaging.

Return procedure for SI6562CDQ-T1-GE3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …