Vishay Siliconix SI7252ADP-T1-GE3
- Part No.:
- SI7252ADP-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FET, MOSFET Arrays
- Package:
- PowerPAK® SO-8 Dual
- Datasheet:
-
SI7252ADP-T1-GE3.pdf
- Description:
- MOSFET 2N-CH 100V 9.3A PPAK SO8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI7252ADP-T1-GE3 from Vishay Siliconix is a dual N-channel 100 V (D-S) TrenchFET® power MOSFET in PowerPAK® SO-8 Dual package, with RDS(on) = 0.0186 Ω at VGS = 10 V, Qg = 13.1 nC typ., and continuous drain current ID = 28.7 A at TC = 25 °C. It serves as a high-efficiency synchronous rectifier or half-bridge switch in DC/DC converters.
For engineers reviewing the SI7252ADP-T1-GE3 datasheet, SI7252ADP-T1-GE3 pinout, SI7252ADP-T1-GE3 application, or SI7252ADP-T1-GE3 equivalent, key selection criteria include its dual-N-channel configuration, low gate charge for PWM optimization, 100 % Rg and UIS tested reliability, thermal resistance RthJC = 3.7 °C/W max, and compatibility with surface-mount reflow per JEDEC J-STD-020.
Technical Context
This device integrates two matched N-channel enhancement-mode MOSFETs in a single leadless PowerPAK SO-8 Dual package, sharing no internal connection between channels - each channel operates independently with isolated source, gate, and drain terminals. Its TrenchFET® process delivers low RDS(on) and fast switching with tr = 5–12 ns and tf = 5–10 ns under defined test conditions.
The MOSFETs feature a body diode with VSD = 0.78–1.1 V at IS = 5 A and reverse recovery time trr = 37–74 ns, enabling efficient freewheeling in synchronous buck topologies. Absolute maximum VGS = ±20 V and avalanche-rated IAS = 10 A support robust gate drive and transient energy handling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 100 V - supports input rails up to 48 V nominal DC/DC systems with margin for voltage spikes |
| RDS(on) max @ 10 V | 0.0186 Ω - enables <1.9 W conduction loss at 10 A, critical for high-current POL converters |
| Qg typ. | 13.1 nC - reduces gate drive power and allows higher PWM frequency without excessive driver loss |
| ID continuous @ TC = 25 °C | 28.7 A - supports >100 W output power in compact thermally managed layouts |
| RthJC max | 3.7 °C/W - enables direct heatsinking to PCB copper or external metal core for thermal management |
| VGS(th) | 2–4 V - ensures reliable turn-on with standard 5 V or 3.3 V logic-level gate drivers |
| tr/tf | 5–12 ns / 5–10 ns - minimizes switching transition losses in 300 kHz–1 MHz SMPS designs |
Pinout & Package
SI7252ADP-T1-GE3 uses the PowerPAK® SO-8 Dual package: 6.15 mm × 5.15 mm × 1.04 mm, leadless, with exposed drain pads on bottom for thermal performance. The package has eight terminals arranged in dual-channel layout with independent gate, source, and drain connections per channel.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Source 1 (S1) | Return path for Channel 1; electrically isolated from S2 - requires separate PCB routing |
| 2 | Gate 1 (G1) | Control input for Channel 1; driven by dedicated gate driver or controller output |
| 3 | Drain 1 (D1) | High-side or low-side switching node for Channel 1; connected to exposed copper pad on bottom |
| 4 | Source 2 (S2) | Return path for Channel 2; independent of S1 - enables floating or common-source configurations |
| 5 | Gate 2 (G2) | Control input for Channel 2; fully decoupled from G1 to prevent crosstalk |
| 6 | Drain 2 (D2) | Switching node for Channel 2; tied to second exposed drain pad - supports dual-phase or interleaved operation |
| 7, 8 | Drain 1 / Drain 2 (D1/D2) | Bottom-side exposed copper pads - primary thermal path to PCB; must be soldered to thermal land |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® technology | Delivers industry-leading RDS(on) × Qg figure-of-merit for high-frequency efficiency |
| PWM-optimized switching | Low Crss (6 pF) and balanced Ciss/Coss ratio reduce Miller-induced shoot-through risk |
| 100 % Rg and UIS tested | Ensures gate robustness and single-pulse avalanche immunity up to 5 mJ (EAS) |
| PowerPAK SO-8 Dual package | Reduces board area vs. two discrete SO-8 devices while maintaining thermal separation between channels |
| Lead (Pb)-free and halogen-free | Complies with RoHS Directive 2011/65/EU and JEDEC JS709E material requirements |
Applications
| Server VRM | Industrial DC/DC Converter |
|---|---|
Use Scenario: High-density 12 V input to 0.8–3.3 V output point-of-load regulation in rack-mounted servers. IC Role / Device Role / Timing Role: Dual N-channel synchronous rectifier in multiphase buck converter - one channel per phase leg. Use Value: Low RDS(on) and Qg minimize conduction and switching losses, enabling >95 % efficiency at 30 A/channel. | Use Scenario: Isolated 48 V to 12 V intermediate bus converter in factory automation PLCs. IC Role / Device Role / Timing Role: Primary-side active clamp switch and secondary-side synchronous rectifier in active-clamp forward topology. Use Value: Independent gate control and avalanche rating allow safe operation during transformer reset and load transients. |
| Telecom PSU | Automotive ADAS Power Module |
Use Scenario: 54 V telecom rectified input to 12 V/5 V distribution in base station power supplies. IC Role / Device Role / Timing Role: Half-bridge high-side and low-side switches in resonant LLC secondary synchronous rectification stage. Use Value: Matched channel parameters ensure balanced current sharing; low VSD reduces freewheeling loss in discontinuous conduction mode. | Use Scenario: Compact 12 V input to 3.3 V/5 V power for radar sensor ECUs in automotive ADAS systems. IC Role / Device Role / Timing Role: Dual-output buck controller companion MOSFET pair powering imaging SoC and interface ICs. Use Value: -55 °C to +150 °C operating range and AEC-Q101 stress-tested construction meet automotive environmental requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-N-channel 100 V MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si7210DN-T1-GE3 | RDS(on) = 0.025 Ω @ 10 V; Qg = 10.5 nC; same PowerPAK SO-8 Dual package | Higher RDS(on) increases conduction loss but lower Qg improves high-frequency switching efficiency | Select when prioritizing gate drive simplicity over peak current capability |
| IRF7341TRPBF | RDS(on) = 0.022 Ω @ 10 V; Qg = 22 nC; SO-8 package with gull-wing leads | Leaded package offers easier manual rework but higher parasitic inductance and inferior thermal resistance (RthJC = 5.5 °C/W) | Select only if legacy SO-8 footprint compatibility or hand-soldering is required |
Compared with Si7210DN-T1-GE3 and IRF7341TRPBF, SI7252ADP-T1-GE3 delivers the lowest RDS(on) and best thermal performance in its class, making it optimal for space-constrained, high-current DC/DC where junction temperature rise must be minimized.
Availability
SI7252ADP-T1-GE3 is available at Aetrix Electronics and suitable for server VRM, industrial DC/DC converter, and telecom PSU applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI7252ADP-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in MOSFETs, diodes, optoelectronics, and passive components with emphasis on power efficiency and reliability.
The SI7252ADP-T1-GE3 belongs to Vishay's TrenchFET® Gen IV dual-MOSFET product line, engineered specifically for high-frequency, high-current synchronous rectification and half-bridge switching in enterprise and industrial power conversion.
FAQ
What is the maximum continuous drain current rating for SI7252ADP-T1-GE3 at 70 °C case temperature?
The SI7252ADP-T1-GE3 supports 23 A continuous drain current (ID) at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This derating reflects thermal limits under steady-state conduction and assumes proper PCB copper area and airflow. At ambient temperature (TA = 25 °C), the rating drops to 9.3 A due to higher junction-to-ambient thermal resistance.
Does SI7252ADP-T1-GE3 have integrated ESD protection on its gate terminals?
SI7252ADP-T1-GE3 does not include on-chip ESD protection diodes. Gate-body leakage (IGSS) is specified at ≤100 nA at ±20 V, confirming absence of clamping structures. External gate resistors and TVS diodes are recommended in high-noise environments. The device passes 100 % Rg testing, verifying gate oxide integrity, but system-level ESD design remains the responsibility of the end user.
Can SI7252ADP-T1-GE3 be used in linear mode (as a pass transistor)?
SI7252ADP-T1-GE3 is not characterized or guaranteed for linear-mode operation. Its Safe Operating Area (SOA) graph shows DC and pulsed limits only up to VDS = 100 V and ID = 28.7 A, with no extended linear region data. The RDS(on) parameter applies only in saturation; using it in the ohmic region risks thermal runaway due to positive temperature coefficient and lack of SOA validation beyond pulse conditions.
What is the body diode reverse recovery charge (Qrr) for SI7252ADP-T1-GE3, and how does it impact synchronous rectifier performance?
The SI7252ADP-T1-GE3 body diode exhibits Qrr = 53–106 nC at IF = 5 A, dI/dt = 100 A/μs, and TJ = 25 °C. This value directly contributes to switching loss during commutation in synchronous rectifiers. Lower Qrr reduces reverse recovery current overshoot and associated EMI, making SI7252ADP-T1-GE3 suitable for high-frequency (>500 kHz) buck converters where diode conduction time is minimized.
Is the PowerPAK SO-8 Dual package of SI7252ADP-T1-GE3 compatible with standard SO-8 reflow profiles?
Yes - SI7252ADP-T1-GE3 follows JEDEC J-STD-020D.3 for leadless packages, with peak reflow temperature of 260 °C (10 s). The PowerPAK SO-8 Dual requires precise stencil design for the bottom-exposed drain pads (pins 7 and 8); insufficient solder paste volume causes voiding and thermal degradation. Vishay document 73257 provides full profile details and solder joint acceptance criteria.
SI7252ADP-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® SO-8 Dual
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- MOSFET (Metal Oxide)
- Configuration:
- 2 N-Channel (Dual)
- FET Feature:
- -
- Drain to Source Voltage (Vdss):
- 100V
- Current - Continuous Drain (Id) @ 25°C:
- 9.3A (Ta), 28.7A (Tc)
- Rds On (Max) @ Id, Vgs:
- 18.6mOhm @ 10A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 26.5nC @ 10V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1266pF @ 50V
- Power - Max:
- 3.6W (Ta), 33.8W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8 Dual
SI7252ADP-T1-GE3 FAQ
1.How can I place an order for SI7252ADP-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI7252ADP-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI7252ADP-T1-GE3 reliable?
The price and inventory of SI7252ADP-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI7252ADP-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SI7252ADP-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI7252ADP-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI7252ADP-T1-GE3?
SI7252ADP-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI7252ADP-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI7252ADP-T1-GE3?
For technical support, including SI7252ADP-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI7252ADP-T1-GE3 requirements.
6.How does Aetrix verify that SI7252ADP-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SI7252ADP-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI7252ADP-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SI7252ADP-T1-GE3?
All SI7252ADP-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SI7252ADP-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI7252ADP-T1-GE3 part is unused and in its original packaging.
Return procedure for SI7252ADP-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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