Vishay Siliconix SI7382DP-T1-E3
- Part No.:
- SI7382DP-T1-E3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SI7382DP-T1-E3.pdf
- Description:
- MOSFET N-CH 30V 14A PPAK SO-8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI7382DP-T1-E3 from Vishay Siliconix is an N-channel enhancement-mode Power MOSFET in PowerPAK® SO-8 package, optimized for low-side DC/DC conversion with 30 V VDS, 4.7 mΩ RDS(on) at VGS = 10 V, and 24 A continuous drain current - deployed in notebook, server, and workstation power stages.
For engineers reviewing the SI7382DP-T1-E3 datasheet, SI7382DP-T1-E3 pinout, SI7382DP-T1-E3 application, or SI7382DP-T1-E3 equivalent, key selection criteria include ultra-low on-resistance, Qg-optimized switching, thermal performance matching DPAK, lead-free compliance, and compatibility with standard SO-8 PCB footprints.
Technical Context
This MOSFET uses Vishay's High-Density TrenchFET® Gen II technology to achieve 4.7 mΩ RDS(on) at 10 V gate drive and 6.2 mΩ at 4.5 V, enabling high-efficiency synchronous rectification in POL converters. Its gate threshold voltage (1.3–3.0 V) supports logic-level and 5 V gate drivers.
The PowerPAK SO-8 package features exposed drain pads on the bottom surface, delivering 1.8 °C/W typical junction-to-case thermal resistance and 20–25 °C/W junction-to-ambient (t ≤ 10 s), enabling higher power density than standard SO-8 while maintaining identical footprint and pinout.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source blocking voltage for 12 V input rail systems with margin. |
| RDS(on) @ VGS = 10 V | 4.7 mΩ - Enables <1 W conduction loss at 24 A, critical for high-current low-voltage output stages. |
| RDS(on) @ VGS = 4.5 V | 6.2 mΩ - Ensures robust operation with 5 V gate drivers and maintains efficiency in partial-gate-drive conditions. |
| Qg | 27–40 nC - Low total gate charge reduces driver power loss and enables fast switching up to ~1 MHz. |
| ID (continuous, TJ = 150 °C) | 24 A - Sustained current capability at elevated junction temperature for thermally constrained designs. |
| RthJC | 1.8 °C/W (typ.) - Thermal path from die to exposed drain pad enables direct heat transfer to PCB copper, matching DPAK performance. |
| VGS(th) | 1.3–3.0 V - Threshold range ensures reliable turn-on with standard logic-level drivers and avoids false triggering. |
Pinout & Package
SI7382DP-T1-E3 is housed in a leadless PowerPAK® SO-8 package (6.15 mm × 5.15 mm × 1.07 mm), featuring an exposed drain pad on the bottom surface for enhanced thermal conduction. It shares the same footprint and pinout as standard SO-8, enabling drop-in replacement without PCB redesign.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate | Control terminal; accepts 0–20 V gate drive; 0.47–1.43 Ω gate resistance aids EMI control and dV/dt management. |
| 2 (S) | Source | Reference node for gate drive; tied to power ground in low-side switch configuration. |
| 3 (S) | Source | Second source connection; paralleled with Pin 2 to reduce source inductance and improve current sharing. |
| 4 (S) | Source | Third source connection; further lowers source loop inductance for high di/dt applications like POL converters. |
| 5 (D) | Drain | Main power output terminal; connected to exposed bottom pad for thermal and current conduction. |
| 6 (D) | Drain | Second drain connection; electrically and thermally tied to Pin 5 and bottom pad. |
| 7 (D) | Drain | Third drain connection; increases current-carrying capacity and improves thermal spreading across PCB copper. |
| 8 (D) | Drain | Fourth drain connection; completes quad-drain layout for minimal RDS(on) and optimal thermal dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low RDS(on) | 4.7 mΩ @ 10 V enables >95 % efficiency in 5 V/20 A buck stages with minimal thermal derating. |
| Qg-optimized design | 27–40 nC total gate charge allows fast turn-on/off with low gate driver power consumption and reduced switching loss. |
| PowerPAK® SO-8 package | 1.07 mm profile and exposed drain pad deliver DPAK-equivalent thermal resistance (1.8 °C/W) in SO-8 footprint. |
| 100 % Rg tested | Guaranteed gate resistance (0.47–1.43 Ω) ensures consistent switching behavior and predictable EMI signature. |
| Lead (Pb)-free and RoHS compliant | T1-E3 suffix denotes lead-free termination compatible with IPC-J-STD-020 reflow profiles up to 255 °C peak. |
Applications
| Server VRM Output Stage | Notebook CPU Core Supply |
|---|---|
Use Scenario: High-current, high-frequency buck converter supplying 1.0–1.3 V to multi-core Xeon processors with dynamic load steps up to 100 A/µs. IC Role / Device Role: Low-side synchronous rectifier in dual-phase interleaved topology. Use Value: 4.7 mΩ RDS(on) minimizes conduction loss at 40 A per phase; PowerPAK thermal performance keeps TJ < 115 °C under full load. |
Use Scenario: Compact 3-phase core regulator powering Intel Core i7/i9 CPUs in ultrabooks with strict height (<1.2 mm) and thermal constraints. IC Role / Device Role: Low-side switch in 500 kHz–1 MHz buck stage with 3.3 V or 5 V input. Use Value: 1.07 mm profile fits thin form factors; 6.2 mΩ RDS(on) at 4.5 V ensures full efficiency with 5 V gate drivers. |
| Workstation POL Module | GPU Memory Rail Converter |
Use Scenario: Point-of-load converter delivering 0.8–1.2 V at up to 60 A to FPGA or ASIC in industrial workstations with ambient up to 70 °C. IC Role / Device Role: Secondary-side switch in multiphase buck with external PWM controller. Use Value: 24 A continuous rating and 56 °C/W steady-state RthJA allow stable operation without forced air cooling. |
Use Scenario: High-density 3-phase converter for GDDR6 memory rails (1.35 V, 45 A) in AI accelerators where board space is limited. IC Role / Device Role: Low-side MOSFET in compact 12 mm × 12 mm module with integrated inductor. Use Value: Quad-drain layout and exposed pad enable >3 W power dissipation in 100 mm² footprint; Qg optimization supports 1.2 MHz switching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si7850DP-T1-E3 | 30 V, 3.3 mΩ @ 10 V, 30 A ID, higher Qg (52 nC), same PowerPAK SO-8 package | Better conduction loss but slower switching; suited for lower-frequency, higher-current VRMs | Select Si7850DP-T1-E3 when RDS(on) priority outweighs switching speed; verify gate driver capability for 52 nC Qg. |
| IRLHS6342TRPBF | 30 V, 5.2 mΩ @ 10 V, 22 A ID, SO-8 package (not PowerPAK), higher RthJA (60 °C/W) | Limited thermal headroom; requires larger copper area or airflow for same current | Choose IRLHS6342TRPBF only if legacy SO-8 land pattern must be reused without thermal pad modification. |
Compared with SI7382DP-T1-E3, Si7850DP-T1-E3 delivers lower conduction loss but demands more gate drive energy, while IRLHS6342TRPBF sacrifices thermal performance for broader distributor availability - SI7382DP-T1-E3 balances RDS(on), Qg, and thermal capability in a production-validated package.
Availability
SI7382DP-T1-E3 is available at Aetrix Electronics and suitable for notebook CPU core supplies, server VRMs, and workstation POL modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for SI7382DP-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in power MOSFETs, diodes, and optoelectronics with emphasis on high-reliability, high-efficiency solutions for computing and industrial markets.
The Si7382DP belongs to Vishay's PowerPAK® SO-8 trench MOSFET family, engineered specifically for high-current, high-frequency DC/DC conversion in space-constrained computing power supplies.
FAQ
What is the maximum continuous drain current for SI7382DP-T1-E3 at 70 °C ambient?
The SI7382DP-T1-E3 supports 19 A continuous drain current at TA = 70 °C (TJ = 150 °C), as specified in its Absolute Maximum Ratings table. This rating assumes proper PCB copper area for thermal dissipation - using ≥1 in² of 2 oz copper on the drain pad sustains this current without exceeding junction temperature limits. The SI7382DP-T1-E3 datasheet confirms this value under "Continuous Drain Current (TJ = 150 °C)" with ambient derating.
Is SI7382DP-T1-E3 pin-compatible with standard SO-8 MOSFETs?
Yes, SI7382DP-T1-E3 is fully pin-compatible with standard SO-8 packages: it uses identical 1.27 mm pitch, 6.15 mm × 5.15 mm outline, and pin 1–8 assignment (G-S-S-S-D-D-D-D). Vishay explicitly states in AN821 that PowerPAK SO-8 "can be substituted directly for a standard SO-8 package." However, the exposed drain pad on the bottom requires appropriate solder paste stencil and thermal pad layout - the SI7382DP-T1-E3 footprint must include a large copper pour connected to the drain net.
What is the gate threshold voltage range for SI7382DP-T1-E3?
The SI7382DP-T1-E3 has a gate threshold voltage (VGS(th)) range of 1.3 V to 3.0 V, measured at VDS = VGS and ID = 250 µA. This range ensures reliable turn-on with 3.3 V and 5 V logic-level drivers while preventing spurious conduction due to noise. The SI7382DP-T1-E3 specification sheet lists this under "MOSFET Specifications" with test conditions clearly defined.
Does SI7382DP-T1-E3 support 4.5 V gate drive in production designs?
Yes, SI7382DP-T1-E3 is fully characterized and rated for 4.5 V gate drive: its RDS(on) is guaranteed at 6.2 mΩ max at VGS = 4.5 V and ID = 21 A. This makes it suitable for 5 V gate driver ICs and microcontroller GPIOs without level-shifting. The SI7382DP-T1-E3 datasheet provides both 10 V and 4.5 V RDS(on) values in the Product Summary and Electrical Characteristics tables.
What is the recommended reflow profile for SI7382DP-T1-E3?
The SI7382DP-T1-E3 requires a lead-free reflow profile with peak temperature of 255 °C ± 0 °C, time above 217 °C between 60–150 s, and ramp-down rate ≤6 °C/s. Vishay document 73257 specifies this exact profile; the SI7382DP-T1-E3 is qualified to JEDEC J-STD-020 standards. Deviation risks voiding warranty and compromising solder joint integrity on the exposed drain pad.
SI7382DP-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 14A (Ta)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 4.7mOhm @ 24A, 10V
- Vgs(th) (Max) @ Id:
- 3V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 40 nC @ 4.5 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- -
- FET Feature:
- -
- Power Dissipation (Max):
- 1.8W (Ta)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SI7382DP-T1-E3 FAQ
1.How can I place an order for SI7382DP-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI7382DP-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI7382DP-T1-E3 reliable?
The price and inventory of SI7382DP-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI7382DP-T1-E3 is usually 5 days.
3.What payment methods are accepted for SI7382DP-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI7382DP-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI7382DP-T1-E3?
SI7382DP-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI7382DP-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI7382DP-T1-E3?
For technical support, including SI7382DP-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI7382DP-T1-E3 requirements.
6.How does Aetrix verify that SI7382DP-T1-E3 is sourced from the original manufacturer or authorized distributors?
All SI7382DP-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI7382DP-T1-E3 meets industry standards.
7.What is the process for return or replacement of SI7382DP-T1-E3?
All SI7382DP-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SI7382DP-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI7382DP-T1-E3 part is unused and in its original packaging.
Return procedure for SI7382DP-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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