Vishay Siliconix SI7772DP-T1-GE3
- Part No.:
- SI7772DP-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SI7772DP-T1-GE3.pdf
- Description:
- MOSFET N-CH 30V 35.6A PPAK SO-8
- Quantity:
- Payment:

- Shipping:

Inventory:5,710
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI7772DP-T1-GE3 from Vishay Siliconix is an N-channel 30 V (D-S) TrenchFET® Gen III power MOSFET with monolithically integrated Schottky diode in a PowerPAK® SO-8 package. It delivers RDS(on) of 0.0130 Ω at VGS = 10 V and 0.0165 Ω at VGS = 4.5 V, supports 35.6 A continuous drain current at TC = 25 °C, and is optimized for low-side notebook system power switching.
For engineers reviewing the SI7772DP-T1-GE3 datasheet, SI7772DP-T1-GE3 pinout, SI7772DP-T1-GE3 application, or SI7772DP-T1-GE3 equivalent, key selection criteria include its SkyFET® integration (MOSFET + Schottky), thermal performance matching DPAK (RthJC = 3.5 °C/W), 8.3 nC gate charge at 4.5 V, body diode reverse recovery time of 17–34 ns, and compatibility with standard SO-8 PCB footprints.
Technical Context
This device implements a monolithic SkyFET® architecture combining a TrenchFET® Gen III silicon die with an integrated Schottky diode on a single substrate - eliminating parasitic inductance and enabling fast, low-loss synchronous rectification. Its gate threshold voltage (1.2–2.5 V) and low RDS(on) support efficient 4.5 V logic-level drive in battery-powered systems.
The PowerPAK® SO-8 package features exposed copper drain pads on the bottom side for direct thermal conduction to the PCB, achieving RthJC = 3.5 °C/W (typical) and RthJA = 27 °C/W (typical, t ≤ 10 s). Unlike standard SO-8, it uses the full footprint for die area - enabling larger silicon than conventional SO-8 while maintaining pin-to-pin compatibility.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source blocking voltage; suitable for 3.3 V/5 V/12 V rail switching in portable computing. |
| RDS(on) @ VGS = 10 V | 0.0130 Ω - Enables <1.3 W conduction loss at 10 A, critical for thermally constrained notebook designs. |
| RDS(on) @ VGS = 4.5 V | 0.0165 Ω - Ensures robust operation with 4.5 V gate drive from common PWM controllers. |
| Qg @ VGS = 4.5 V | 8.3 nC - Low gate charge reduces driver power and switching losses in high-frequency DC-DC converters. |
| ID (continuous, TC = 25 °C) | 35.6 A - High current capability supports multi-phase VRMs and high-power load switches. |
| VSD (body diode) | 0.48–0.65 V - Low forward voltage of integrated Schottky reduces freewheeling losses vs. standard MOSFET body diodes. |
| trr | 17–34 ns - Fast reverse recovery minimizes shoot-through risk and EMI in synchronous buck topologies. |
Pinout & Package
SI7772DP-T1-GE3 is housed in a leadless PowerPAK® SO-8 package (5.15 mm × 6.15 mm × 1.04 mm), featuring exposed drain terminals on the bottom for enhanced thermal transfer. The top-side pinout matches standard SO-8: pins 1–4 are source (S), pin 5 is gate (G), and pins 6–8 are drain (D).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | Source (S) | Common source connection for internal MOSFET and Schottky cathode; electrically tied to PCB ground plane. |
| 5 | Gate (G) | Control terminal for MOSFET channel; requires <2.5 V threshold and <100 nA leakage per spec. |
| 6, 7, 8 | Drain (D) | High-current drain node shared by MOSFET and Schottky anode; bottom-side copper pad provides primary thermal path. |
Key Features
| Feature | Design Value |
|---|---|
| SkyFET® monolithic integration | Co-located MOSFET + Schottky on single die eliminates bond-wire inductance and improves diode recovery consistency. |
| 100 % Rg and UIS tested | Guarantees gate resistance (0.3–2.6 Ω) and ruggedness against unclamped inductive switching events up to 15 A/11.25 mJ. |
| PowerPAK® SO-8 footprint compatibility | Direct replacement for standard SO-8 layouts without PCB redesign; leverages same land pattern but delivers DPAK-level thermal performance. |
| Exposed drain thermal pad | Bottom-side copper enables junction-to-board RthJB ≈ 1.0 °C/W - reducing die temperature rise by ~40 °C vs. standard SO-8 under identical 2.7 W dissipation. |
Applications
| Server VRM Low-Side Switch | Notebook CPU Core Power |
|---|---|
Use Scenario: High-current, high-frequency synchronous buck converter in dual-processor server motherboards. IC Role / Device Role / Timing Role: Low-side power switch handling up to 35.6 A continuous current with fast body-diode commutation during dead-time. Use Value: Integrated Schottky reduces reverse recovery losses by >50% vs. discrete MOSFET+diode solutions, lowering total converter loss by ~0.8 W at 20 A. | Use Scenario: Core voltage regulation for Intel Core i7/i9 processors in ultrabooks with strict thermal envelope limits. IC Role / Device Role / Timing Role: Synchronous rectifier in 500 kHz–1 MHz multiphase buck stage, driven by dedicated gate controller. Use Value: RDS(on) = 0.0165 Ω at 4.5 V ensures stable operation with 5 V PWM drivers, while PowerPAK thermal design keeps TJ < 110 °C at full load. |
| USB-C PD Power Path | Industrial PLC I/O Protection |
Use Scenario: Bidirectional power path switch enabling simultaneous charging and data negotiation in USB-C PD 3.0 systems. IC Role / Device Role / Timing Role: Reverse-polarity protected, low-RDS(on) load switch controlling 20 V/5 A power delivery path. Use Value: 30 V VDS rating and 0.0130 Ω RDS(on) ensure <130 mW conduction loss at 5 A, meeting USB-C thermal safety requirements. | Use Scenario: Overcurrent-protected 24 V DC input module in programmable logic controllers with field-wiring protection. IC Role / Device Role / Timing Role: Protected high-side switch with integrated reverse-battery protection via Schottky clamp. Use Value: Body diode VSD = 0.48–0.65 V clamps reverse transients below 1 V, preventing damage to downstream analog front-end circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel MOSFET with integrated Schottky applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si7446DP-T1-GE3 | Same PowerPAK SO-8 package; lower RDS(on) (0.0095 Ω @ 10 V) but higher Qg (12.5 nC); no integrated Schottky. | Requires external Schottky for synchronous rectification; better for pure switching where diode recovery is managed externally. | Select when lowest conduction loss dominates and external diode layout is acceptable. |
| Si7850DP-T1-GE3 | Higher VDS (40 V); slightly higher RDS(on) (0.0175 Ω @ 4.5 V); same SkyFET® integration and PowerPAK package. | Supports wider input ranges (e.g., 24 V industrial rails); marginally higher conduction loss at 12 V systems. | Select when 40 V blocking is required for transient immunity in 24 V applications. |
Compared with Si7446DP-T1-GE3, SI7772DP-T1-GE3 trades 0.0035 Ω higher RDS(on) for integrated Schottky functionality and 4.2 nC lower Qg at 4.5 V - simplifying layout and improving light-load efficiency. Against Si7850DP-T1-GE3, SI7772DP-T1-GE3 offers tighter 30 V rating for cost-sensitive 12 V/19 V notebook rails with identical thermal behavior.
Availability
SI7772DP-T1-GE3 is available at Aetrix Electronics and suitable for notebook system power, server VRM low-side switching, and USB-C PD power path applications requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production lots.
Supply support for SI7772DP-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in power MOSFETs, diodes, and optoelectronics with emphasis on high-reliability, high-efficiency silicon solutions.
The SI7772DP-T1-GE3 belongs to Vishay's SkyFET® family - engineered specifically for high-density, thermally constrained DC-DC conversion in portable computing and enterprise infrastructure, where monolithic MOSFET+Schottky integration delivers measurable efficiency and layout advantages.
FAQ
What is the maximum continuous drain current for SI7772DP-T1-GE3 at 70 °C case temperature?
The maximum continuous drain current for SI7772DP-T1-GE3 is 28.5 A at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This derating reflects thermal limitations of the PowerPAK® SO-8 package under sustained power dissipation. SI7772DP-T1-GE3 maintains this rating due to its low RthJC of 3.5 °C/W, enabling higher current than standard SO-8 equivalents at elevated temperatures.
Does SI7772DP-T1-GE3 require a heatsink in typical notebook applications?
No, SI7772DP-T1-GE3 does not require an external heatsink in typical notebook applications. Its PowerPAK® SO-8 package transfers heat directly through the exposed drain pad to the PCB, achieving RthJA = 27 °C/W (typical, t ≤ 10 s). At 12.9 A ambient-rated current and 2.5 W dissipation, board-level copper acts as sufficient heatsink - verified in Vishay's 1" × 1" FR4 test board data. SI7772DP-T1-GE3 is designed for passive thermal management.
How does the integrated Schottky diode in SI7772DP-T1-GE3 improve synchronous buck efficiency?
The integrated Schottky diode in SI7772DP-T1-GE3 reduces reverse recovery charge (Qrr = 7–14 nC) and time (trr = 17–34 ns) versus standard MOSFET body diodes, minimizing dead-time losses and EMI. With VSD = 0.48–0.65 V, it cuts freewheeling conduction loss by ~40% compared to discrete solutions. SI7772DP-T1-GE3 achieves this without added layout area or parasitic inductance - directly enhancing light-load and transient efficiency in buck converters.
Is SI7772DP-T1-GE3 compatible with standard SO-8 reflow soldering profiles?
Yes, SI7772DP-T1-GE3 is compatible with standard lead-free reflow profiles, including peak temperature of 255 °C (±0 °C tolerance) for ≤30 s, per Vishay document 73257. Its PowerPAK® SO-8 construction passes JEDEC J-STD-020 moisture sensitivity Level 1 testing. SI7772DP-T1-GE3 requires no special process adjustments beyond standard SO-8 reflow - though manual soldering with iron is not recommended due to its leadless design.
What is the gate-source leakage current specification for SI7772DP-T1-GE3?
The gate-source leakage current (IGSS) for SI7772DP-T1-GE3 is ±100 nA maximum at VGS = ±20 V and TA = 25 °C, per the Electrical Specifications table. This low leakage ensures minimal gate drive current demand and stable turn-on/turn-off behavior in high-impedance PWM control circuits. SI7772DP-T1-GE3 maintains this specification across its full operating temperature range (-55 to +150 °C).
SI7772DP-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- SkyFET®, TrenchFET®
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 35.6A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 13mOhm @ 15A, 10V
- Vgs(th) (Max) @ Id:
- 2.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 28 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1084 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 3.9W (Ta), 29.8W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SI7772DP-T1-GE3 FAQ
1.How can I place an order for SI7772DP-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI7772DP-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI7772DP-T1-GE3 reliable?
The price and inventory of SI7772DP-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI7772DP-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SI7772DP-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI7772DP-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI7772DP-T1-GE3?
SI7772DP-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI7772DP-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI7772DP-T1-GE3?
For technical support, including SI7772DP-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI7772DP-T1-GE3 requirements.
6.How does Aetrix verify that SI7772DP-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SI7772DP-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI7772DP-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SI7772DP-T1-GE3?
All SI7772DP-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SI7772DP-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI7772DP-T1-GE3 part is unused and in its original packaging.
Return procedure for SI7772DP-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI7772DP-T1-GE3 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
