Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Vishay Siliconix SI7804DN-T1-GE3

Name: SI7804DN-T1-GE3
Brand: Vishay Siliconix
SKU: SI7804DN-T1-GE3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI7804DN-T1-GE3

Manufacturer:: Vishay Siliconix

Category:: FETs, MOSFETs

Package:: PowerPAK® 1212-8

Datasheet:: SI7804DN-T1-GE3.pdf

Description:: MOSFET N-CH 30V 6.5A PPAK1212-8

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:9,870

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI7804DN-T1-GE3 from Vishay Siliconix is a N-channel 30-V (D-S) TrenchFET® Power MOSFET in PowerPAK® 1212-8 package, delivering R_DS(on) = 0.0185 Ω at V_GS = 10 V and 0.030 Ω at V_GS = 4.5 V, with continuous drain current up to 10 A (T_A = 25 °C), optimized for high-efficiency DC/DC conversion stages.

For engineers reviewing the SI7804DN-T1-GE3 datasheet, SI7804DN-T1-GE3 pinout, SI7804DN-T1-GE3 application, or SI7804DN-T1-GE3 equivalent, this device offers verified thermal performance (R_thJC = 4.5 °C/W typ.), 100 % R_g tested gate resistance, and halogen-free/lead-free compliance per IEC 61249-2-21 - critical for compact, thermally constrained power designs.

Technical Context

This MOSFET employs trench-gate silicon technology enabling low on-resistance and fast switching with Q_g = 8.7–13 nC (V_DS = 15 V, V_GS = 5 V, I_D = 10 A) and t_d(off) = 32–50 ns under standard test conditions. Its gate threshold voltage (V_GS(th)) ranges 0.8–1.8 V, supporting robust 4.5 V logic-level drive.

The PowerPAK 1212-8 package features exposed drain pads on the bottom side for direct thermal conduction, achieving R_thJA = 28–35 °C/W (t ≤ 10 s) and R_thJC = 4.5–6.0 °C/W (steady state), significantly outperforming SO-8 and TSSOP-8 equivalents in thermal impedance.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	30 V - Maximum drain-source blocking voltage for 12 V and 24 V input DC/DC systems.
R_DS(on) @ 10 V	0.0185 Ω - Enables <185 mW conduction loss at 10 A, reducing heat generation in high-current synchronous rectifiers.
R_DS(on) @ 4.5 V	0.030 Ω - Ensures full enhancement with standard 5 V microcontroller GPIO or PWM controller outputs.
I_D (continuous)	10 A @ T_A = 25 °C - Supports ≥8 A load current in typical 1"×1" FR4 PCB layouts without forced air.
Q_g	8.7–13 nC - Low total gate charge minimizes driver power loss and enables >1 MHz switching in high-frequency converters.
R_thJC	4.5 °C/W (typ.) - Direct junction-to-case path allows efficient heat transfer to PCB copper, limiting ΔT to ~4.8 °C at 2 W dissipation.
V_GS(th)	0.8–1.8 V - Guaranteed turn-on with 3.3 V logic, compatible with modern low-voltage control ICs and avoiding shoot-through risk.

Pinout & Package

SI7804DN-T1-GE3 uses the leadless PowerPAK® 1212-8 package (3.30 mm × 3.30 mm × 1.07 mm), with exposed drain terminals on the bottom surface and top-side signal terminals. Thermal performance relies on proper PCB land pattern design per Vishay AN822.

Pin/Terminal	Circuit Role	Design Meaning
1, 2, 3, 4	Source (S)	Four parallel source terminals - reduce source inductance and improve current sharing in high-di/dt switching.
5, 6, 7, 8	Drain (D)	Four exposed drain pads on bottom - primary thermal path to PCB; require soldered copper pour for optimal R_thJA.
Gate (G)	Control input	Single top-side gate terminal - designed for low-inductance gate loop layout; R_g tested 0.5–2.2 Ω ensures consistent switching timing.

Key Features

Feature	Design Value
TrenchFET® architecture	Delivers industry-leading R_DS(on) × area efficiency - 0.0185 Ω at 10 V in 10.9 mm² footprint, enabling smaller converter footprints.
PowerPAK® 1212-8 package	Reduces R_thJC by >80 % vs. TSSOP-8 - junction temperature rise limited to <5 °C above board temp at 2 W, preserving r_DS(on) stability.
100 % R_g tested	Guarantees gate resistance between 0.5–2.2 Ω - eliminates variation in turn-on/turn-off delay and reduces EMI sensitivity across production lots.
Halogen-free & Pb-free	Complies with IEC 61249-2-21 and RoHS - qualified for automotive and industrial applications requiring strict material declarations.
Fast switching dynamics	t_d(on) = 8–15 ns, t_f = 14–25 ns - supports clean zero-voltage switching (ZVS) transitions in resonant topologies up to 2 MHz.

Applications

Point-of-Load (POL) Regulator	Synchronous Buck Converter
Use Scenario: High-density server VRMs delivering 3.3 V/10 A to FPGA core rails with <10 mm² board space constraint. IC Role / Device Role: Synchronous rectifier switch replacing Schottky diode to minimize conduction loss and improve efficiency. Use Value: 0.0185 Ω R_DS(on) cuts rectifier loss by >60 % vs. 40 V Schottky, enabling >94 % efficiency at full load without heatsink.	Use Scenario: Industrial PLC power module converting 24 V input to 5 V/6 A output with tight thermal budget (<60 °C ambient). IC Role / Device Role: Low-side synchronous FET in fixed-frequency 500 kHz buck stage. Use Value: R_thJC = 4.5 °C/W keeps junction <85 °C at 2 W dissipation, eliminating derating and enabling single-layer PCB layout.
USB-C PD Power Delivery	Motor Drive Half-Bridge
Use Scenario: 20 V/3 A USB-C PD sink circuit requiring bidirectional current capability and low-profile solution. IC Role / Device Role: Reverse-blocking switch in path-control FET configuration with integrated body diode. Use Value: V_SD = 0.75–1.2 V at I_S = 2.9 A ensures <3.5 W reverse conduction loss, meeting USB-C thermal limits without airflow.	Use Scenario: 12 V BLDC motor driver for HVAC fan where PCB height must be <1.2 mm and EMI must be minimized. IC Role / Device Role: Low-side switch in half-bridge leg, driven by isolated gate driver with 4.5 V output. Use Value: V_GS(th) = 0.8–1.8 V guarantees reliable turn-on at 4.5 V drive, preventing shoot-through during PWM dead-time transitions.

Point-of-Load (POL) Regulator

Synchronous Buck Converter

Use Scenario: High-density server VRMs delivering 3.3 V/10 A to FPGA core rails with <10 mm² board space constraint.

IC Role / Device Role: Synchronous rectifier switch replacing Schottky diode to minimize conduction loss and improve efficiency.

Use Value: 0.0185 Ω R_DS(on) cuts rectifier loss by >60 % vs. 40 V Schottky, enabling >94 % efficiency at full load without heatsink.

Use Scenario: Industrial PLC power module converting 24 V input to 5 V/6 A output with tight thermal budget (<60 °C ambient).

IC Role / Device Role: Low-side synchronous FET in fixed-frequency 500 kHz buck stage.

Use Value: R_thJC = 4.5 °C/W keeps junction <85 °C at 2 W dissipation, eliminating derating and enabling single-layer PCB layout.

USB-C PD Power Delivery

Motor Drive Half-Bridge

Use Scenario: 20 V/3 A USB-C PD sink circuit requiring bidirectional current capability and low-profile solution.

IC Role / Device Role: Reverse-blocking switch in path-control FET configuration with integrated body diode.

Use Value: V_SD = 0.75–1.2 V at I_S = 2.9 A ensures <3.5 W reverse conduction loss, meeting USB-C thermal limits without airflow.

Use Scenario: 12 V BLDC motor driver for HVAC fan where PCB height must be <1.2 mm and EMI must be minimized.

IC Role / Device Role: Low-side switch in half-bridge leg, driven by isolated gate driver with 4.5 V output.

Use Value: V_GS(th) = 0.8–1.8 V guarantees reliable turn-on at 4.5 V drive, preventing shoot-through during PWM dead-time transitions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si7850DP-T1-GE3	Higher V_DS = 40 V, R_DS(on) = 0.022 Ω @ 10 V, same PowerPAK 1212-8 package and pinout.	Better suited for 36 V input industrial DC/DC; marginally higher conduction loss at 30 V systems.	Select when system max V_IN exceeds 30 V or long-term reliability at elevated voltage stress is required.
DMN3025LSD-13	Dual N-channel in SO-8 package; R_DS(on) = 0.025 Ω @ 10 V per channel; R_thJA = 62 °C/W (steady state).	Larger footprint (5.0 × 6.0 mm), higher thermal resistance - requires larger copper area or airflow for same power handling.	Choose only if dual-FET integration is needed and board space allows SO-8; avoid for thermally aggressive POL designs.

Compared with Si7850DP-T1-GE3, SI7804DN-T1-GE3 provides lower R_DS(on) and tighter V_GS(th) tolerance at 30 V rating, improving efficiency in 12–24 V systems; versus DMN3025LSD-13, it delivers 4× better thermal resistance in 40 % less area, enabling higher power density without thermal compromise.

Availability

SI7804DN-T1-GE3 is available at Aetrix Electronics and suitable for point-of-load regulators, synchronous buck converters, USB-C PD power delivery, and motor drive half-bridges requiring stable component supply, halogen-free compliance, and high thermal performance in ultra-compact layouts.

Supply support for SI7804DN-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency and reliability.

The Si78xxDN series targets high-frequency, high-density DC/DC conversion, leveraging TrenchFET® and PowerPAK® technologies to deliver lowest R_DS(on) per mm² for space-constrained industrial and computing power supplies.

FAQ

What is the maximum continuous drain current for SI7804DN-T1-GE3 at 70 °C ambient temperature?

The SI7804DN-T1-GE3 supports 7.5 A continuous drain current at T_A = 70 °C with no derating, as specified in the Absolute Maximum Ratings table. This value assumes standard mounting on a 1" × 1" FR4 board with adequate copper pour on the drain pads. At higher ambient temperatures, current must be reduced per the derating curve in Figure 5 of the datasheet to maintain T_J ≤ 150 °C. The SI7804DN-T1-GE3's low R_thJC enables this high current capability without external heatsinking.

Does SI7804DN-T1-GE3 support 3.3 V gate drive?

Yes, SI7804DN-T1-GE3 is fully compatible with 3.3 V logic-level gate drive due to its guaranteed V_GS(th) range of 0.8–1.8 V and R_DS(on) = 0.030 Ω at V_GS = 4.5 V. While not fully enhanced at 3.3 V, it achieves usable conduction (R_DS(on) ≈ 0.045 Ω typ. per characterization curves), making it suitable for 3.3 V microcontroller-driven low-power switches. For full enhancement and minimal loss, 4.5 V or higher drive is recommended. The SI7804DN-T1-GE3's low threshold ensures reliable turn-on even with gate driver voltage drop.

What is the avalanche energy rating for SI7804DN-T1-GE3?

The SI7804DN-T1-GE3 has a rated single-pulse avalanche energy (E_AS) of 11 mJ, measured with L = 0.1 mH and I_AS = 15 A. This rating applies under controlled test conditions (T_J = 25 °C, pulse width ≤ 300 µs) and reflects the device's ability to absorb transient inductive energy without failure. It is not intended for repetitive avalanche operation. Designers should verify layout parasitics and clamp voltage margins when using SI7804DN-T1-GE3 in circuits prone to inductive switching transients.

Can SI7804DN-T1-GE3 be reworked using a soldering iron?

No - manual soldering with a soldering iron is explicitly not recommended for SI7804DN-T1-GE3 due to its leadless PowerPAK® 1212-8 package. The exposed copper drain pads require precise reflow profile control (peak 240 °C ± 5 °C, 20–40 s dwell) per Vishay document 73257. Hand-soldering risks insufficient wetting, voiding, or thermal damage to the die attach. Rework must use infrared or hot-air reflow stations calibrated to the JEDEC J-STD-020 profile. The SI7804DN-T1-GE3's construction demands process-controlled thermal management.

Is SI7804DN-T1-GE3 suitable for synchronous rectification in DC/DC converters?

Yes, SI7804DN-T1-GE3 is specifically optimized for synchronous rectification in buck, boost, and buck-boost converters. Its low R_DS(on) (0.0185 Ω @ 10 V), fast switching (t_d(off) = 32–50 ns), and low Q_g (8.7–13 nC) minimize both conduction and switching losses. The body diode's V_SD = 0.75–1.2 V at 2.9 A ensures low reverse recovery loss, while the 100 % R_g test guarantees consistent timing across units. In a 12 V → 3.3 V converter, SI7804DN-T1-GE3 improves efficiency by 2–3 % over Schottky alternatives.

SI7804DN-T1-GE3 Specifications

Product attributes: Attribute value

Manufacturer:: Vishay Siliconix

Series:: TrenchFET®

Package/Case:: PowerPAK® 1212-8

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 30 V

Current - Continuous Drain (Id) @ 25°C:: 6.5A (Ta)

Drive Voltage (Max Rds On, Min Rds On):: 4.5V, 10V

Rds On (Max) @ Id, Vgs:: 18.5mOhm @ 10A, 10V

Vgs(th) (Max) @ Id:: 1.8V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 13 nC @ 5 V

Vgs (Max):: ±20V

Input Capacitance (Ciss) (Max) @ Vds:: -

FET Feature:: -

Power Dissipation (Max):: 1.5W (Ta)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: PowerPAK® 1212-8

SI7804DN-T1-GE3 FAQ

1.How can I place an order for SI7804DN-T1-GE3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI7804DN-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI7804DN-T1-GE3 reliable?

The price and inventory of SI7804DN-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI7804DN-T1-GE3 is usually 5 days.

3.What payment methods are accepted for SI7804DN-T1-GE3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI7804DN-T1-GE3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI7804DN-T1-GE3?

SI7804DN-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI7804DN-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI7804DN-T1-GE3?

For technical support, including SI7804DN-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI7804DN-T1-GE3 requirements.

6.How does Aetrix verify that SI7804DN-T1-GE3 is sourced from the original manufacturer or authorized distributors?

All SI7804DN-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI7804DN-T1-GE3 meets industry standards.

7.What is the process for return or replacement of SI7804DN-T1-GE3?

All SI7804DN-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SI7804DN-T1-GE3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI7804DN-T1-GE3 part is unused and in its original packaging.

Return procedure for SI7804DN-T1-GE3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …