Vishay Siliconix SIE808DF-T1-E3
- Part No.:
- SIE808DF-T1-E3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- 10-PolarPAK® (L)
- Datasheet:
-
SIE808DF-T1-E3.pdf
- Description:
- MOSFET N-CH 20V 60A 10POLARPAK
- Quantity:
- Payment:

- Shipping:

Inventory:3,517
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Product details
Overview
SIE808DF-T1-E3 from Vishay Siliconix is an N-channel 20-V TrenchFET® Gen II Power MOSFET in PolarPAK® package, delivering RDS(on) = 0.0016 Ω at VGS = 10 V and 220 A silicon-limited continuous drain current, optimized for low-side DC/DC conversion and synchronous rectification in high-current VRM applications.
For engineers reviewing the SIE808DF-T1-E3 datasheet, SIE808DF-T1-E3 pinout, SIE808DF-T1-E3 application, or SIE808DF-T1-E3 equivalent, this page provides verified thermal resistance (RthJC = 0.8 °C/W max to drain top), gate charge (Qg = 46 nC typ. at 4.5 V), body diode recovery (trr = 56 ns), package layout details, and two validated alternative MOSFETs for similar high-efficiency power stage designs.
Technical Context
This MOSFET uses a trench-based silicon process with low Qgd/Qgs ratio to suppress shoot-through in synchronous buck topologies. Its PolarPAK® Option L package features double-sided cooling via top-exposed drain terminals (pins 1, 5, 6, 10) and source-connected bottom terminals (pins 2, 3, 7, 8), enabling junction-to-case thermal resistance as low as 0.8 °C/W.
The device is rated for ±20 V gate-source voltage, supports 100 % Rg and UIS testing, and meets RoHS and halogen-free requirements per IEC 61249-2-21. It operates across -55 °C to +150 °C junction temperature range with guaranteed VGS(th) of 1.5–3.0 V and body diode forward voltage of 0.8–1.2 V at 10 A.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 20 V - Maximum drain-source blocking voltage for low-voltage synchronous rectification. |
| RDS(on) | 0.0016 Ω @ VGS = 10 V - Enables <1.6 mΩ conduction loss at 25 A, critical for >95 % efficiency in 12 V input VRMs. |
| ID (Silicon Limit) | 220 A - Supports high-current power stages without silicon saturation under pulse conditions. |
| Qg | 46 nC @ VGS = 4.5 V - Low gate charge reduces driver power loss and enables fast switching in high-frequency DC/DC converters. |
| RthJC (Drain) | 0.8 °C/W max - Enables direct heatsinking to PCB copper or external cooler via top-side drain pads for thermal management. |
| trr | 56 ns - Fast body diode recovery minimizes reverse recovery losses during dead-time in synchronous rectifiers. |
| VGS(th) | 1.5–3.0 V - Ensures reliable turn-on with standard 3.3 V or 5 V gate drivers while avoiding false triggering. |
Pinout & Package
PolarPAK® Option L is a leadless, surface-mount package with 10 terminals: four top-side drain pads (pins 1, 5, 6, 10), four bottom-side source pads (pins 2, 3, 7, 8), one top-side gate pad (pin 4), and one bottom-side gate pad (pin 9). The top surface is electrically connected to pins 1, 5, 6, and 10 (drain), enabling double-sided thermal and electrical connection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 5, 6, 10 | Drain (Top-Side) | Electrically common drain connections on top surface; used for thermal interface and high-current output routing. |
| 2, 3, 7, 8 | Source (Bottom-Side) | Electrically common source connections on bottom surface; provide low-inductance return path and PCB thermal spreading. |
| 4 | Gate (Top-Side) | Primary gate control terminal on top surface; requires short, low-inductance trace to driver for optimal switching. |
| 9 | Gate (Bottom-Side) | Secondary gate terminal on bottom surface; enables gate loop optimization and reduced parasitic inductance in high-speed layouts. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low RthJC (Drain) | 0.8 °C/W max enables direct top-side heatsinking-critical for high-power density VRM modules. |
| Low Qgd/Qgs ratio | Reduces Miller-induced shoot-through risk in synchronous buck converters operating above 500 kHz. |
| 100 % Rg tested | Ensures consistent gate resistance (0.9–1.35 Ω) for predictable switching behavior and driver design. |
| Double-sided cooling architecture | Simultaneous thermal path through top (drain) and bottom (source) surfaces improves steady-state thermal performance by >30 % vs. standard SO-8. |
| TrenchFET® Gen II silicon | Delivers 30 % lower RDS(on) than prior generation at same die size-enabling smaller footprint or higher current capability. |
Applications
| Server VRM Power Stage | GPU Voltage Regulator |
|---|---|
Use Scenario: High-current, multi-phase buck converter supplying core voltage to Intel Xeon or AMD EPYC processors. IC Role / Device Role / Timing Role: Low-side synchronous rectifier in each phase, conducting during bottom switch interval with minimal conduction loss. Use Value: 0.0016 Ω RDS(on) at 10 V reduces conduction loss to <1 W per phase at 100 A, improving overall VRM efficiency and reducing thermal load on PCB. | Use Scenario: Compact, high-density voltage regulator for NVIDIA or AMD discrete graphics cards requiring rapid transient response. IC Role / Device Role / Timing Role: Low-side MOSFET in 300–600 kHz synchronous buck stage, handling peak currents up to 120 A per phase. Use Value: 46 nC gate charge at 4.5 V allows fast turn-on with low-driver power consumption, supporting tight duty-cycle control during GPU load transients. |
| Industrial DC/DC Converter | Telecom Base Station PSU |
Use Scenario: 48 V to 12 V isolated intermediate bus converter in factory automation equipment. IC Role / Device Role / Timing Role: Secondary-side synchronous rectifier in LLC or phase-shifted full-bridge topology. Use Value: 56 ns body diode reverse recovery time minimizes energy loss during zero-voltage switching transitions, increasing converter efficiency by ~0.8 % at full load. | Use Scenario: High-reliability 54 V to 12 V non-isolated buck converter powering RF power amplifiers in 4G/5G macro base stations. IC Role / Device Role / Timing Role: Low-side switch in multiphase VRM delivering stable 12 V/200 A output with tight regulation. Use Value: Junction-to-case thermal resistance of 0.8 °C/W allows mounting directly to aluminum heatsink, maintaining TJ < 125 °C at full load without forced air. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel 20-V power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRL8721PBF | RDS(on) = 0.0022 Ω @ 4.5 V; Qg = 32 nC; SO-8 package; RthJA = 50 °C/W (vs. 20–24 °C/W for SIE808DF-T1-E3) | Limited to ≤60 A continuous due to SO-8 package thermal constraints; not suitable for >100 A VRM phases. | Choose only for cost-sensitive, lower-current (<60 A) applications where board space permits larger thermal footprint. |
| SiR872DP-T1-GE3 | RDS(on) = 0.0015 Ω @ 10 V; Qg = 52 nC; PowerPAK® 1212-8 package; RthJC = 1.2 °C/W (drain) | Higher gate charge increases driver loss; single-sided cooling limits thermal headroom in high-power density designs. | Select when existing layout uses PowerPAK® 1212-8 footprint and thermal margin exceeds 15 °C/W to ambient. |
Compared with IRL8721PBF and SiR872DP-T1-GE3, the SIE808DF-T1-E3 delivers superior thermal performance (0.8 °C/W RthJC), lower gate charge at 4.5 V (46 nC), and double-sided cooling-making it uniquely suited for >100 A, high-density VRM and GPU power stages where junction temperature control is critical.
Availability
SIE808DF-T1-E3 is available at Aetrix Electronics and suitable for server VRM power stages, GPU voltage regulators, and industrial DC/DC converters requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for SIE808DF-T1-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency, thermal robustness, and reliability.
The PolarPAK® product line was developed specifically for high-current, high-efficiency power conversion applications-including VRMs, GPU supplies, and telecom PSUs-where ultra-low RDS(on), minimized thermal resistance, and double-sided cooling are essential design requirements.
FAQ
What is the maximum continuous drain current rating for SIE808DF-T1-E3 under typical PCB mounting conditions?
The SIE808DF-T1-E3 has a silicon-limited continuous drain current of 220 A, but its package-limited rating is 60 A when mounted on a 1" × 1" FR4 board. This 60 A limit reflects thermal constraints of the PolarPAK® package under standard JEDEC test conditions-not electrical capability. For higher current operation, the SIE808DF-T1-E3 must be used with enhanced thermal management such as direct heatsinking to the top-side drain pads or multilayer copper planes. Always verify actual board-level thermal performance using measured RthJA values.
Does SIE808DF-T1-E3 support gate drive voltages below 4.5 V, and what is its threshold behavior?
Yes, the SIE808DF-T1-E3 specifies VGS(th) between 1.5 V and 3.0 V, making it compatible with 3.3 V logic-level gate drivers. At VGS = 4.5 V, it delivers RDS(on) = 0.0025 Ω-suitable for high-efficiency operation in modern VRMs. However, its on-resistance rises significantly below 3.5 V, so operation below that voltage is not recommended for power-switching applications. The SIE808DF-T1-E3 also exhibits a negative VGS(th) temperature coefficient (−7.3 mV/°C), ensuring inherent current sharing stability in paralleled configurations.
How does the PolarPAK® package of SIE808DF-T1-E3 differ from conventional SO-8 or PowerPAK® packages in thermal performance?
The SIE808DF-T1-E3 PolarPAK® Option L package achieves RthJC = 0.8 °C/W (max) to the drain top surface-more than 3× better than typical SO-8 (RthJC ≈ 3.0 °C/W) and ~30 % better than PowerPAK® 1212-8 (RthJC ≈ 1.2 °C/W). This is enabled by its top-exposed drain structure and dual thermal paths: heat flows vertically through both top (drain) and bottom (source) metal surfaces. Unlike conventional packages, the SIE808DF-T1-E3 allows simultaneous thermal interface to heatsink and PCB, enabling compact, high-power-density designs without thermal bottlenecks.
Is SIE808DF-T1-E3 suitable for avalanche-rated applications, and what is its rated energy capability?
Yes, the SIE808DF-T1-E3 is 100 % tested for Unclamped Inductive Switching (UIS) and rated for single-pulse avalanche energy EAS = 61 mJ at TJ = 25 °C. Its avalanche current rating is IAS = 35 A with L = 0.1 mH. These ratings apply under defined test conditions and confirm ruggedness against inductive switching transients in synchronous rectifier and motor drive applications. However, repeated avalanche operation degrades reliability-designers should implement snubbers or clamp circuits to avoid sustained avalanche stress on the SIE808DF-T1-E3.
What are the soldering requirements and rework limitations for SIE808DF-T1-E3?
The SIE808DF-T1-E3 is a leadless PolarPAK® package with exposed copper terminations; its recommended peak soldering temperature is 260 °C per JEDEC J-STD-020. Manual soldering with an iron is explicitly not recommended due to thermal mass and lack of visual solder fillet formation at the singulated copper tips. Rework requires specialized hot-air or infrared systems calibrated for leadless components. The SIE808DF-T1-E3 datasheet (Doc. 73739) specifies that adequate bottom-side interconnection is achieved without visible fillets-relying instead on controlled solder volume and reflow profile per Doc. 73257.
SIE808DF-T1-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- 10-PolarPAK® (L)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 60A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.6mOhm @ 25A, 10V
- Vgs(th) (Max) @ Id:
- 3V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 155 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 8800 pF @ 10 V
- FET Feature:
- -
- Power Dissipation (Max):
- 5.2W (Ta), 125W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-PolarPAK® (L)
SIE808DF-T1-E3 FAQ
1.How can I place an order for SIE808DF-T1-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIE808DF-T1-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIE808DF-T1-E3 reliable?
The price and inventory of SIE808DF-T1-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIE808DF-T1-E3 is usually 5 days.
3.What payment methods are accepted for SIE808DF-T1-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIE808DF-T1-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIE808DF-T1-E3?
SIE808DF-T1-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIE808DF-T1-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIE808DF-T1-E3?
For technical support, including SIE808DF-T1-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIE808DF-T1-E3 requirements.
6.How does Aetrix verify that SIE808DF-T1-E3 is sourced from the original manufacturer or authorized distributors?
All SIE808DF-T1-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIE808DF-T1-E3 meets industry standards.
7.What is the process for return or replacement of SIE808DF-T1-E3?
All SIE808DF-T1-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIE808DF-T1-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIE808DF-T1-E3 part is unused and in its original packaging.
Return procedure for SIE808DF-T1-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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