Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Vishay Siliconix SIE820DF-T1-GE3

Name: SIE820DF-T1-GE3
Brand: Vishay Siliconix
SKU: SIE820DF-T1-GE3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SIE820DF-T1-GE3

Manufacturer:: Vishay Siliconix

Category:: FETs, MOSFETs

Package:: 10-PolarPAK® (S)

Datasheet:: SIE820DF-T1-GE3.pdf

Description:: MOSFET N-CH 20V 50A 10POLARPAK

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,375

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SIE820DF-T1-GE3 from Vishay Siliconix is an N-channel 20-V TrenchFET® Power MOSFET in a PolarPAK® package, featuring R_DS(on) = 0.0035 Ω at V_GS = 4.5 V, 136 A silicon-limited continuous drain current, and ultra-low Q_gd for minimized switching losses in high-frequency synchronous rectification.

For engineers reviewing the SIE820DF-T1-GE3 datasheet, SIE820DF-T1-GE3 pinout, SIE820DF-T1-GE3 application, or SIE820DF-T1-GE3 equivalent, this device is selected for VRM and DC/DC converter designs requiring double-sided cooling, low gate charge (43 nC at 4.5 V), and halogen-free, RoHS-compliant packaging with top-exposed drain thermal path.

Technical Context

This MOSFET uses Vishay's proprietary TrenchFET® process with Extremely Low Q_gd WFET technology to reduce Miller capacitance and suppress shoot-through risk via low Q_gd/Q_gs ratio. Its PolarPAK® package integrates a leadframe-based encapsulation where the top surface connects directly to pins 1, 5, 6, and 10 - all tied to the drain - enabling efficient double-sided thermal management.

The device operates with V_GS(th) = 0.6–2.0 V, supports 100% R_g and UIS testing, and delivers 45 mJ single-pulse avalanche energy. Thermal resistance is specified as R_thJC(Drain) = 1.0 °C/W (typ), confirming suitability for high-power density board-level thermal design.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	20 V - Maximum drain-source blocking voltage compatible with 12 V input bus systems and point-of-load converters.
R_DS(on)	0.0035 Ω at V_GS = 4.5 V - Enables <1.5 W conduction loss at 60 A, critical for high-efficiency VRM output stages.
I_D (Silicon Limit)	136 A - Supports high-current synchronous rectification without derating due to die capability.
Q_g	43 nC at V_GS = 4.5 V - Reduces gate drive power and enables >1 MHz switching in compact DC/DC designs.
R_thJC (Drain)	1.0 °C/W (typ) - Confirms effective thermal coupling to heatsink or PCB copper through top-exposed drain terminals.
V_GS(th)	0.6–2.0 V - Ensures reliable turn-on with standard 3.3 V or 5 V gate drivers in logic-level applications.
C_iss	4300 pF - Defines input capacitance affecting gate driver sizing and EMI filter design in hard-switched topologies.

Pinout & Package

PolarPAK® is a leadless, top-exposed drain package with 10 terminals. The top metal surface is electrically connected to pins 1, 5, 6, and 10 - all drain nodes - enabling dual-side thermal interface. Bottom-side soldering provides mechanical and electrical connection to source and gate terminals.

Pin/Terminal	Circuit Role	Design Meaning
1, 5, 6, 10	Drain (D)	Top-exposed drain terminals - primary thermal path and high-current return; must be soldered to large copper pour or heatsink.
2, 3, 4, 7, 8, 9	Source (S)	Source connections distributed across six bottom-side pins - minimize source inductance and improve current sharing in parallel configurations.
4	Gate (G)	Single dedicated gate terminal - located adjacent to source pins to reduce gate loop inductance and suppress ringing.

Key Features

Feature	Design Value
Ultra-low Q_gd/Q_gs ratio	Reduces Miller-induced turn-on risk during high-dV/dt commutation, improving reliability in synchronous buck converters.
Top-exposed PolarPAK® drain	Enables double-sided cooling - thermal resistance to case (drain) is 1.0 °C/W, allowing >100 W dissipation with minimal ΔT.
100% R_g and UIS tested	Ensures gate robustness against transient overvoltage and ruggedness under unclamped inductive switching stress.
Halogen-free & RoHS compliant	Fulfills IEC 61249-2-21 and EU Directive 2002/95/EC requirements for environmentally constrained industrial and computing applications.
TrenchFET® silicon technology	Delivers lower R_DS(on) × area than planar MOSFETs - achieves 0.0035 Ω in compact 5 mm × 6 mm footprint.

Applications

VRM Output Stage	High-Density DC/DC Converter
Use Scenario: Primary synchronous rectifier in server CPU voltage regulator modules delivering up to 200 A at 0.8–1.8 V. IC Role / Device Role / Timing Role: Low-side power switch operating in continuous conduction mode with 300–1000 kHz PWM control. Use Value: 0.0035 Ω R_DS(on) minimizes conduction loss; 43 nC Q_g enables fast switching with low gate drive loss.	Use Scenario: Secondary-side synchronous rectifier in telecom 48 V input, 12 V output isolated DC/DC bricks. IC Role / Device Role / Timing Role: High-current, low-voltage power switch in forward or LLC resonant topology secondary side. Use Value: Top-exposed drain allows direct thermal interface to heatsink; 136 A silicon limit supports peak current surges without derating.
Synchronous Rectification	Industrial Motor Drive Inverter
Use Scenario: Secondary-side switch in AC/DC adapter or USB PD 100 W charger with GaN primary controller. IC Role / Device Role / Timing Role: Unidirectional power switch conducting during freewheeling interval with body diode reverse recovery managed by low Q_rr. Use Value: 101 ns trr and 100 nC Q_rr reduce switching loss and EMI during diode commutation.	Use Scenario: Half-bridge low-side switch in 24 V BLDC motor gate driver stage for factory automation actuators. IC Role / Device Role / Timing Role: Fast-switching N-channel MOSFET controlled by isolated gate driver with 10 V gate bias. Use Value: V_GS(th) range (0.6–2.0 V) ensures compatibility with 3.3 V logic-level drivers; 45 mJ EAS withstands inductive flyback energy.

VRM Output Stage

High-Density DC/DC Converter

Use Scenario: Primary synchronous rectifier in server CPU voltage regulator modules delivering up to 200 A at 0.8–1.8 V.

IC Role / Device Role / Timing Role: Low-side power switch operating in continuous conduction mode with 300–1000 kHz PWM control.

Use Value: 0.0035 Ω R_DS(on) minimizes conduction loss; 43 nC Q_g enables fast switching with low gate drive loss.

Use Scenario: Secondary-side synchronous rectifier in telecom 48 V input, 12 V output isolated DC/DC bricks.

IC Role / Device Role / Timing Role: High-current, low-voltage power switch in forward or LLC resonant topology secondary side.

Use Value: Top-exposed drain allows direct thermal interface to heatsink; 136 A silicon limit supports peak current surges without derating.

Synchronous Rectification

Industrial Motor Drive Inverter

Use Scenario: Secondary-side switch in AC/DC adapter or USB PD 100 W charger with GaN primary controller.

IC Role / Device Role / Timing Role: Unidirectional power switch conducting during freewheeling interval with body diode reverse recovery managed by low Q_rr.

Use Value: 101 ns trr and 100 nC Q_rr reduce switching loss and EMI during diode commutation.

Use Scenario: Half-bridge low-side switch in 24 V BLDC motor gate driver stage for factory automation actuators.

IC Role / Device Role / Timing Role: Fast-switching N-channel MOSFET controlled by isolated gate driver with 10 V gate bias.

Use Value: V_GS(th) range (0.6–2.0 V) ensures compatibility with 3.3 V logic-level drivers; 45 mJ EAS withstands inductive flyback energy.

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel 20-V power MOSFET applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IRLHS6342TRPBF	R_DS(on) = 0.0037 Ω @ 4.5 V; SO-8 package; no top-exposed drain; R_thJC = 3.5 °C/W.	Lacks double-sided cooling capability; limited to single-side PCB thermal management.	Select when board space constraints favor SO-8 and thermal load ≤ 30 W.
SIS840DN-T1-GE3	R_DS(on) = 0.0028 Ω @ 4.5 V; same PolarPAK® package; higher Q_g = 58 nC; 30 V rating.	Higher voltage rating adds margin but increases gate drive energy; better for 24 V systems.	Select when 30 V V_DS headroom is required or lower R_DS(on) justifies higher Q_g.

Compared with IRLHS6342TRPBF, SIE820DF-T1-GE3 offers 2.5× lower junction-to-case thermal resistance and superior high-current capability; versus SIS840DN-T1-GE3, it trades 0.7 mΩ higher R_DS(on) for 15 nC lower Q_g, favoring high-frequency operation in VRM applications.

Availability

SIE820DF-T1-GE3 is available at Aetrix Electronics and suitable for VRM output stages, high-density DC/DC converters, and synchronous rectification circuits requiring stable component supply, halogen-free compliance, and double-sided thermal management.

Supply support for SIE820DF-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics for power management and signal conditioning.

The SIE820DF-T1-GE3 belongs to Vishay's PolarPAK® TrenchFET® family, engineered specifically for high-current, high-efficiency DC/DC conversion and synchronous rectification in computing, telecom, and industrial power supplies.

FAQ

What is the maximum continuous drain current rating for SIE820DF-T1-GE3?

The SIE820DF-T1-GE3 has a silicon-limited continuous drain current of 136 A at T_J = 150 °C, but its package-limited rating is 50 A at T_C = 25 °C. This dual rating reflects the device's ability to handle high current when thermally managed via its top-exposed drain, while remaining within safe PCB-level limits under standard mounting conditions. Always refer to the thermal derating curves in the SIE820DF-T1-GE3 datasheet for ambient or case temperature adjustments.

Does SIE820DF-T1-GE3 support logic-level gate drive?

Yes, the SIE820DF-T1-GE3 supports logic-level gate drive with a gate-threshold voltage (V_GS(th)) ranging from 0.6 V to 2.0 V, ensuring full enhancement using standard 3.3 V or 5 V controllers. At V_GS = 4.5 V, it achieves its specified R_DS(on) of 0.0035 Ω, making it ideal for modern low-voltage gate driver ICs used in VRM and POL applications. The SIE820DF-T1-GE3 does not require 10 V gate bias for optimal performance.

How is thermal management implemented in the SIE820DF-T1-GE3 PolarPAK® package?

The SIE820DF-T1-GE3 uses a PolarPAK® package with top-exposed drain terminals (pins 1, 5, 6, 10) that serve as the primary thermal path - achieving R_thJC(Drain) = 1.0 °C/W (typ). This allows heat to be extracted from both top and bottom surfaces, enabling double-sided cooling via heatsink contact on top and PCB copper on bottom. The SIE820DF-T1-GE3 requires no exposed die and maintains consistent layout regardless of die size, simplifying thermal design across variants.

Is SIE820DF-T1-GE3 suitable for synchronous rectification in high-frequency converters?

Yes, the SIE820DF-T1-GE3 is optimized for synchronous rectification in high-frequency converters, with 43 nC total gate charge at V_GS = 4.5 V and extremely low Q_gd to minimize Miller-induced switching delay and shoot-through risk. Its 101 ns body diode reverse recovery time and 100 nC Q_rr further reduce commutation loss. The SIE820DF-T1-GE3 is widely deployed in >500 kHz VRMs and USB PD chargers where fast, efficient low-side switching is critical.

What halogen-free and environmental compliance certifications apply to SIE820DF-T1-GE3?

The SIE820DF-T1-GE3 is certified halogen-free per IEC 61249-2-21 and fully compliant with the RoHS Directive 2002/95/EC. The "-GE3" suffix explicitly denotes lead-free and halogen-free construction, verified through material declarations and manufacturing process controls by Vishay Siliconix. No brominated flame retardants or chlorine-based compounds are used in the molding compound or terminations of the SIE820DF-T1-GE3.

SIE820DF-T1-GE3 Specifications

Product attributes: Attribute value

Manufacturer:: Vishay Siliconix

Series:: TrenchFET®

Package/Case:: 10-PolarPAK® (S)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

FET Type:: N-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 20 V

Current - Continuous Drain (Id) @ 25°C:: 50A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 2.5V, 4.5V

Rds On (Max) @ Id, Vgs:: 3.5mOhm @ 18A, 4.5V

Vgs(th) (Max) @ Id:: 2V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 143 nC @ 10 V

Vgs (Max):: ±12V

Input Capacitance (Ciss) (Max) @ Vds:: 4300 pF @ 10 V

FET Feature:: -

Power Dissipation (Max):: 5.2W (Ta), 104W (Tc)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 10-PolarPAK® (S)

SIE820DF-T1-GE3 FAQ

1.How can I place an order for SIE820DF-T1-GE3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SIE820DF-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SIE820DF-T1-GE3 reliable?

The price and inventory of SIE820DF-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIE820DF-T1-GE3 is usually 5 days.

3.What payment methods are accepted for SIE820DF-T1-GE3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIE820DF-T1-GE3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SIE820DF-T1-GE3?

SIE820DF-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SIE820DF-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SIE820DF-T1-GE3?

For technical support, including SIE820DF-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIE820DF-T1-GE3 requirements.

6.How does Aetrix verify that SIE820DF-T1-GE3 is sourced from the original manufacturer or authorized distributors?

All SIE820DF-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIE820DF-T1-GE3 meets industry standards.

7.What is the process for return or replacement of SIE820DF-T1-GE3?

All SIE820DF-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIE820DF-T1-GE3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SIE820DF-T1-GE3 part is unused and in its original packaging.

Return procedure for SIE820DF-T1-GE3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …