Vishay Siliconix SIR402DP-T1-GE3
- Part No.:
- SIR402DP-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SIR402DP-T1-GE3.pdf
- Description:
- MOSFET N-CH 30V 35A PPAK SO-8
- Quantity:
- Payment:

- Shipping:

Inventory:3,000
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Product details
Overview
SIR402DP-T1-GE3 from Vishay Siliconix is an N-channel 30-V TrenchFET® Power MOSFET in PowerPAK SO-8 package, delivering 35 A continuous drain current at TC = 25 °C, RDS(on) of 0.006 Ω at VGS = 10 V, and 12 nC total gate charge - optimized for high-efficiency synchronous rectification in server DC/DC point-of-load converters.
For engineers reviewing the SIR402DP-T1-GE3 datasheet, SIR402DP-T1-GE3 pinout, SIR402DP-T1-GE3 application, or SIR402DP-T1-GE3 equivalent, key selection criteria include its low RDS(on) at 4.5 V (0.008 Ω), 100 % UIS and Rg tested qualification, lead-free/halogen-free construction, and thermal performance matching DPAK via PowerPAK SO-8's exposed-drain thermal path.
Technical Context
This MOSFET employs trench-gate silicon technology to achieve low on-resistance and fast switching with Qg = 12–21 nC (VGS = 4.5–10 V). Its gate threshold voltage (1.15–2.2 V) enables robust 4.5 V logic-level drive compatibility while maintaining tight VGS(th) temperature coefficient (−6 mV/°C).
The device integrates a body diode with trr = 25–50 ns and Qrr = 17–35 nC, supporting high-frequency synchronous rectification. Thermal design leverages the PowerPAK SO-8's 2.9 °C/W typical RthJC and exposed copper drain pad, enabling junction-to-ambient thermal resistance as low as 25 °C/W under optimized PCB layout.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum blocking voltage for 12 V and 24 V input DC/DC stages |
| RDS(on) | 0.006 Ω @ VGS = 10 V - Enables <1 W conduction loss at 35 A in high-current POL rails |
| ID (Cont.) | 35 A @ TC = 25 °C - Package-limited current rating suitable for multi-phase VRMs |
| Qg | 12 nC @ VGS = 4.5 V - Low gate charge reduces driver power and switching losses below 1 MHz |
| RthJC | 2.9 °C/W - Direct thermal path from die to PCB enables efficient heatsinking without external heatsinks |
| VGS(th) | 1.15–2.2 V - Ensures reliable turn-on with standard 3.3 V/5 V gate drivers and stable operation across −55 to 150 °C |
| trr / Qrr | 25–50 ns / 17–35 nC - Minimizes reverse recovery loss and EMI in synchronous rectifier configurations |
Pinout & Package
PowerPAK SO-8 is a leadless surface-mount package with same footprint and pinout as standard SO-8, featuring an exposed copper drain pad on the bottom for enhanced thermal conduction. Dimensions: 6.15 mm × 5.15 mm × 1.04 mm (L × W × H).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate | Control terminal; accepts 0–20 V drive; 100 % Rg tested for consistent switching timing |
| 2 (S) | Source | Reference node for gate drive and current sensing; tied to power ground in synchronous rectifier topology |
| 3 (S) | Source | Parallel source connection to reduce package inductance and improve current sharing |
| 4 (S) | Source | Third source terminal for low-inductance source return path in high-dI/dt applications |
| 5 (D) | Drain | Main power output terminal; connected to exposed bottom copper pad for thermal and electrical conduction |
| 6 (D) | Drain | Second drain terminal; shares current with Pin 5 and bottom pad to lower RDS(on) and thermal resistance |
| 7 (D) | Drain | Third drain terminal; enhances current handling and thermal spreading across PCB copper area |
| 8 (D) | Drain | Fourth drain terminal; completes quad-drain configuration for minimal voltage drop and hot-spot mitigation |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® architecture | Enables 0.006 Ω RDS(on) at 10 V and 0.008 Ω at 4.5 V - critical for high-efficiency 48 V–12 V intermediate bus conversion |
| 100 % UIS tested | Guarantees ruggedness against inductive switching stress in synchronous buck converters without snubbers |
| Exposed-drain PowerPAK SO-8 | Delivers 2.9 °C/W RthJC - matches DPAK thermal performance while retaining SO-8 board space and reflow compatibility |
| Halogen-free & RoHS-compliant | Fulfills IEC 61249-2-21 and Directive 2002/95/EC - required for server and telecom equipment environmental certification |
| Low Qgd/Qg ratio | Qgd = 4.6 nC / Qg = 12–21 nC - improves Miller immunity and enables stable operation with high-side gate drivers |
Applications
| Server VRM Output Stage | Telecom 48 V Intermediate Bus Converter |
|---|---|
Use Scenario: High-current, high-density voltage regulator module supplying CPU/GPU core power at ≤0.8 V and >100 A per phase. IC Role / Device Role: Low-side synchronous rectifier MOSFET in multiphase buck converter, replacing Schottky diodes. Use Value: 0.006 Ω RDS(on) cuts conduction loss by >40 % vs. legacy SO-8 MOSFETs, enabling higher efficiency at full load and reduced thermal derating. | Use Scenario: Isolated DC/DC brick converting 48 V telecom input to 12 V intermediate bus with >95 % efficiency target. IC Role / Device Role: Secondary-side synchronous rectifier in forward or LLC resonant converter. Use Value: 12 nC Qg at 4.5 V allows clean switching at 500 kHz–1 MHz with minimal gate drive loss and reduced EMI filtering burden. |
| AI Accelerator Board POL Regulator | Industrial PLC Power Supply |
Use Scenario: Compact, high-transient-response point-of-load regulator feeding FPGA or ASIC with dynamic current steps up to 50 A/µs. IC Role / Device Role: High-current, low-inductance synchronous rectifier in dual-phase interleaved buck. Use Value: Quad-source and quad-drain terminals minimize package loop inductance, suppressing voltage overshoot during fast load transients. | Use Scenario: Ruggedized 24 V input power supply for programmable logic controllers operating in extended temperature environments (−40 to 85 °C). IC Role / Device Role: Primary-side high-side switch or secondary-side rectifier in non-isolated buck converter. Use Value: −55 to 150 °C TJ range and 100 % UIS testing ensure reliability under industrial surge and thermal cycling conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel 30-V MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiR402DP-T1-RE3 | Same die and package; differs only in tape-and-reel packaging (RE3 = 3,000 pcs/reel vs. GE3 = 4,000 pcs/reel); identical electrical specs | No functional difference; RE3 used for smaller-volume production runs or prototyping | Select GE3 for high-volume server manufacturing where reel size aligns with SMT line feeder capacity |
| SiR404DP-T1-GE3 | Higher RDS(on): 0.0085 Ω @ 10 V; higher Qg: 14 nC @ 4.5 V; otherwise identical PowerPAK SO-8 footprint and thermal design | Suitable where marginally higher conduction loss is acceptable to reduce gate drive complexity or cost | Choose SiR404DP-T1-GE3 only if system-level thermal analysis confirms adequate margin with +0.5 mΩ RDS(on) increase |
Compared with SiR404DP-T1-GE3, SIR402DP-T1-GE3 delivers lower conduction loss and faster switching, making it preferable for high-efficiency server VRMs; versus SiR402DP-T1-RE3, it offers higher reel quantity for automated assembly throughput without electrical trade-offs.
Availability
SIR402DP-T1-GE3 is available at Aetrix Electronics and suitable for server VRMs, telecom DC/DC converters, and AI accelerator board power delivery requiring stable component supply, long-term lifecycle support, and traceable halogen-free sourcing.
Supply support for SIR402DP-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency and reliability.
The SiR402DP product line targets high-current, high-frequency power conversion in datacenter and communications infrastructure, designed specifically to replace larger packages like DPAK without sacrificing thermal or electrical performance.
FAQ
What is the maximum continuous drain current rating for SIR402DP-T1-GE3 at 70 °C case temperature?
The SIR402DP-T1-GE3 supports 35 A continuous drain current at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This rating is package-limited and remains unchanged from the 25 °C value due to the PowerPAK SO-8's superior thermal design, unlike conventional SO-8 devices that derate significantly above 25 °C. The 35 A rating applies under steady-state conditions with proper PCB copper area.
Does SIR402DP-T1-GE3 support 4.5 V gate drive in synchronous rectifier applications?
Yes, SIR402DP-T1-GE3 is fully characterized for 4.5 V gate drive: RDS(on) is guaranteed at 0.008 Ω (max) with ID = 17.5 A, and total gate charge is 12 nC (typ). Its VGS(th) range of 1.15–2.2 V ensures strong enhancement-mode turn-on at 4.5 V, making it suitable for controller ICs with 4.5 V gate outputs in modern multiphase VRMs and POL converters.
How does the PowerPAK SO-8 package of SIR402DP-T1-GE3 improve thermal performance over standard SO-8?
The SIR402DP-T1-GE3's PowerPAK SO-8 features an exposed copper drain pad on the bottom surface, reducing RthJC to 2.9 °C/W (typ) - comparable to DPAK and ~5× better than standard SO-8. This direct thermal path lowers junction temperature rise by up to 43 °C under identical 2.7 W dissipation, preserving RDS(on) stability and enabling higher current density without forced air cooling.
Is SIR402DP-T1-GE3 qualified for repetitive unclamped inductive switching (UIS)?
Yes, SIR402DP-T1-GE3 undergoes 100 % UIS testing per JEDEC JESD22-A202, with rated avalanche energy EAS = 61 mJ and single-pulse avalanche current IAS = 35 A. This qualification ensures robustness in synchronous buck converters during startup, overload, or control-loop faults where inductive energy must be safely absorbed by the MOSFET without failure.
What are the recommended PCB layout practices for optimal thermal performance of SIR402DP-T1-GE3?
For optimal thermal performance, use the recommended PowerPAK SO-8 land pattern from Vishay Application Note AN826: extend the drain copper area to ≥0.3–0.4 in² (≈200–260 mm²) on inner layers, maintain solid copper on internal power/ground planes, and avoid traces under the package body. The exposed drain pad must be soldered directly to this copper area; no thermal vias are required but can be added for additional heat spreading in constrained layouts.
SIR402DP-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 35A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 6mOhm @ 20A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 42 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1700 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 4.2W (Ta), 36W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SIR402DP-T1-GE3 FAQ
1.How can I place an order for SIR402DP-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIR402DP-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIR402DP-T1-GE3 reliable?
The price and inventory of SIR402DP-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIR402DP-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIR402DP-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIR402DP-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIR402DP-T1-GE3?
SIR402DP-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIR402DP-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIR402DP-T1-GE3?
For technical support, including SIR402DP-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIR402DP-T1-GE3 requirements.
6.How does Aetrix verify that SIR402DP-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIR402DP-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIR402DP-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIR402DP-T1-GE3?
All SIR402DP-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIR402DP-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIR402DP-T1-GE3 part is unused and in its original packaging.
Return procedure for SIR402DP-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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