Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Discrete Semiconductor Products > Transistors > FETs, MOSFETs > FETs, MOSFETs

Vishay Siliconix SIR403EDP-T1-GE3

Name: SIR403EDP-T1-GE3
Brand: Vishay Siliconix
SKU: SIR403EDP-T1-GE3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SIR403EDP-T1-GE3

Manufacturer:: Vishay Siliconix

Category:: FETs, MOSFETs

Package:: PowerPAK® SO-8

Datasheet:: SIR403EDP-T1-GE3.pdf

Description:: MOSFET P-CH 30V 40A PPAK SO-8

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:12,434

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SIR403EDP-T1-GE3 from Vishay Siliconix is a P-channel TrenchFET® power MOSFET in PowerPAK® SO-8 package, rated for -30 V V_DS, 0.0065 Ω R_DS(on) at V_GS = -10 V, and -40 A continuous drain current (T_C = 25 °C). It serves as an efficient adaptor switch or load switch in portable power management systems.

For engineers reviewing the SIR403EDP-T1-GE3 datasheet, SIR403EDP-T1-GE3 pinout, SIR403EDP-T1-GE3 application, or SIR403EDP-T1-GE3 equivalent, key selection criteria include its extended ±25 V gate voltage rating, ultra-low on-resistance at low V_GS (-4.5 V), 100% UIS testing, and thermal performance matching DPAK while retaining SO-8 footprint compatibility.

Technical Context

This device uses trench-gate silicon technology to achieve high channel density and low R_DS(on) with stable threshold voltage (V_GS(th) = -1.2 to -2.8 V) and low gate charge (Q_g = 66 nC typ. at V_GS = -5 V). Its body diode exhibits t_rr = 35 ns and Q_rr = 25 nC, supporting fast switching in synchronous buck or OR-ing configurations.

The PowerPAK SO-8 package features exposed copper drain pads on the bottom side for direct thermal conduction, achieving R_thJC = 1.7 °C/W (typ.) and R_thJA = 20 °C/W (typ., t ≤ 10 s), enabling high-power density without external heatsinks in compact notebook and battery-pack designs.

Key Specifications

Parameter	Value and Actual Design Meaning
V_DS	-30 V - Maximum blocking voltage for negative-rail switching in 3.3 V/5 V/12 V system power paths
R_DS(on) max @ V_GS = -10 V	0.0065 Ω - Enables <1 W conduction loss at 40 A, critical for high-efficiency load switching
R_DS(on) max @ V_GS = -4.5 V	0.0115 Ω - Supports logic-level gate drive from standard microcontroller I/O pins
Q_g typ.	66 nC - Low total gate charge reduces driver power and enables <30 ns turn-on delay with 1 Ω gate resistor
I_D continuous (T_C = 25 °C)	-40 A - Sustains full-rated current with case temperature monitoring, suitable for high-current adapter rails
R_thJC max	2.2 °C/W - Confirms robust thermal path from junction to PCB copper, enabling >50 W dissipation with minimal ΔT
V_GS range	±25 V - Allows safe operation under transient overvoltage conditions in unregulated input stages

Pinout & Package

Package: PowerPAK® SO-8 (leadless, 5.15 mm × 6.15 mm × 1.04 mm), thermally enhanced with exposed drain pad on bottom side. Compatible with standard SO-8 land patterns but optimized using extended drain copper area per AN821 and AN826.

Pin/Terminal	Circuit Role	Design Meaning
1, 2, 3, 5	Source (S)	Four parallel source terminals reduce source inductance and improve current sharing in high-di/dt load-switching
4	Gate (G)	Single gate input with R_g = 0.3–2.6 Ω - supports direct MCU drive or buffered gate control
6, 7, 8, D-Pad	Drain (D)	Eight-terminal drain connection plus bottom-exposed copper pad provides ultra-low thermal resistance and high-current capability

Key Features

Feature	Design Value
TrenchFET® architecture	Delivers 23% lower R_DS(on) vs. planar P-channel MOSFETs of same die size, improving power density
100% UIS tested	Guarantees ruggedness against inductive switching stress without derating, essential for hot-swap and load-dump protection
ESD rating (HBM)	4000 V - Reduces need for external ESD protection in portable end-equipment assembly lines
PowerPAK SO-8 thermal design	Matches DPAK R_thJC (1.7 °C/W) while fitting SO-8 footprint - eliminates board redesign when upgrading from SO-8
Lead (Pb)-free & halogen-free	Complies with RoHS Directive 2011/65/EU and JEDEC JS709E - qualified for industrial and consumer production

Applications

Adaptor Switch	Load Switch for Battery Packs
Use Scenario: AC/DC adapter output stage controlling power delivery to system rail during plug-in/unplug events. IC Role / Device Role / Timing Role: High-side P-channel switch enabling reverse-polarity and overvoltage protection with fast turn-off. Use Value: Ultra-low R_DS(on) minimizes dropout voltage (<300 mV at 20 A), preserving efficiency across wide input voltage range.	Use Scenario: Isolation of Li-ion battery pack from system during charging, fault, or sleep mode. IC Role / Device Role / Timing Role: Load switch providing controlled inrush current limiting and soft-start via gate slew rate control. Use Value: 66 nC Q_g allows precise timing of turn-on/turn-off transitions, reducing surge currents and contact arcing.
Notebook System Power Rail	OR-ing Diode Replacement
Use Scenario: Main 5 V or 3.3 V system rail switching between AC adapter and battery sources. IC Role / Device Role / Timing Role: Bidirectional load switch managing seamless source transition without brownout. Use Value: Body diode V_SD = -0.78 V (typ.) and t_rr = 35 ns enable low-loss reverse conduction during switchover.	Use Scenario: Replacing Schottky diodes in redundant power supply paths to eliminate forward voltage drop. IC Role / Device Role / Timing Role: Active OR-ing controller implementing ideal diode behavior with reverse current blocking. Use Value: R_DS(on) = 0.0065 Ω cuts conduction loss by >85% vs. 0.4 V Schottky, significantly lowering thermal load.

Adaptor Switch

Load Switch for Battery Packs

Use Scenario: AC/DC adapter output stage controlling power delivery to system rail during plug-in/unplug events.

IC Role / Device Role / Timing Role: High-side P-channel switch enabling reverse-polarity and overvoltage protection with fast turn-off.

Use Value: Ultra-low R_DS(on) minimizes dropout voltage (<300 mV at 20 A), preserving efficiency across wide input voltage range.

Use Scenario: Isolation of Li-ion battery pack from system during charging, fault, or sleep mode.

IC Role / Device Role / Timing Role: Load switch providing controlled inrush current limiting and soft-start via gate slew rate control.

Use Value: 66 nC Q_g allows precise timing of turn-on/turn-off transitions, reducing surge currents and contact arcing.

Notebook System Power Rail

OR-ing Diode Replacement

Use Scenario: Main 5 V or 3.3 V system rail switching between AC adapter and battery sources.

IC Role / Device Role / Timing Role: Bidirectional load switch managing seamless source transition without brownout.

Use Value: Body diode V_SD = -0.78 V (typ.) and t_rr = 35 ns enable low-loss reverse conduction during switchover.

Use Scenario: Replacing Schottky diodes in redundant power supply paths to eliminate forward voltage drop.

IC Role / Device Role / Timing Role: Active OR-ing controller implementing ideal diode behavior with reverse current blocking.

Use Value: R_DS(on) = 0.0065 Ω cuts conduction loss by >85% vs. 0.4 V Schottky, significantly lowering thermal load.

Equivalent & Alternatives

The following parts are listed as comparable options for similar P-channel load switch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SiR402EDP-T1-GE3	Same PowerPAK SO-8 package; lower R_DS(on) (0.0052 Ω @ -10 V) but reduced V_GS(th) (-0.9 to -2.2 V) increases risk of partial turn-on at low gate drive	Better efficiency at high current, but requires tighter gate voltage control in 3.3 V logic systems	Select SiR402EDP-T1-GE3 only if gate drive ≥ -5 V is guaranteed and thermal margin exceeds 10 W
IRF7424TRPBF	Standard SO-8 package; higher R_DS(on) (0.012 Ω @ -10 V); R_thJA = 62 °C/W - limits continuous current to ~12 A at TA = 70 °C	Lower cost but unsuitable for >15 A applications without forced air or heatsink	Choose IRF7424TRPBF only for space-tolerant, low-power designs where thermal budget permits 4× higher R_thJA

Compared with SiR402EDP-T1-GE3 and IRF7424TRPBF, SIR403EDP-T1-GE3 delivers optimal balance of low R_DS(on), robust gate threshold, and DPAK-class thermal performance in SO-8 footprint - making it preferred for high-reliability, high-current portable power switches where layout reuse and thermal headroom are critical.

Availability

SIR403EDP-T1-GE3 is available at Aetrix Electronics and suitable for notebook computers, portable battery packs, and AC/DC adaptor switch applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for SIR403EDP-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency and reliability.

The SIR403EDP-T1-GE3 belongs to Vishay's PowerPAK® SO-8 TrenchFET® family, engineered specifically for high-current, low-voltage load switching in space-constrained portable electronics where thermal performance and gate-drive flexibility are paramount.

FAQ

What is the maximum continuous drain current rating for SIR403EDP-T1-GE3 at 70 °C case temperature?

The SIR403EDP-T1-GE3 supports -40 A continuous drain current at T_C = 70 °C, as specified in the Absolute Maximum Ratings table. This rating is limited by package thermal capacity, not silicon, and assumes proper PCB copper layout per AN826 for the PowerPAK SO-8 footprint. The device maintains this current with R_DS(on) = 0.0065 Ω at V_GS = -10 V, resulting in <11.5 W conduction loss.

Does SIR403EDP-T1-GE3 require a gate driver IC for operation with a 3.3 V microcontroller?

No, the SIR403EDP-T1-GE3 can be directly driven by a 3.3 V microcontroller GPIO because its V_GS(th) ranges from -1.2 V to -2.8 V and R_DS(on) remains low (0.0115 Ω max) at V_GS = -4.5 V. However, for fastest switching and lowest Q_g-related losses, a dedicated gate driver is recommended when operating above 10 A or at >100 kHz frequencies.

How does the PowerPAK SO-8 package of SIR403EDP-T1-GE3 improve thermal performance over standard SO-8 MOSFETs?

The PowerPAK SO-8 package of SIR403EDP-T1-GE3 achieves R_thJC = 1.7 °C/W (typ.), matching DPAK performance, versus ~16 °C/W for standard SO-8. This is enabled by an exposed copper drain pad on the bottom side that conducts heat directly into PCB copper, reducing junction-to-board ΔT by up to 40 °C under identical 2.7 W dissipation - verified in AN821 thermal characterization.

Is SIR403EDP-T1-GE3 suitable for reverse polarity protection in automotive accessory circuits?

SIR403EDP-T1-GE3 is not automotive-qualified (AEC-Q101) and operates only to +150 °C junction temperature, below typical automotive under-hood requirements. While its -30 V V_DS and ±25 V V_GS support 12 V system transients, it lacks automotive-grade screening, qualification testing, and guaranteed parametric stability across -40 to +125 °C ambient - use only in non-automotive portable or industrial power rails.

What is the typical body diode reverse recovery time (t_rr) of SIR403EDP-T1-GE3 and how does it affect synchronous rectification?

The SIR403EDP-T1-GE3 has t_rr = 35 ns (typ.) and Q_rr = 25 nC at I_F = -10 A and dI/dt = 100 A/μs. These values enable clean commutation in synchronous buck topologies up to ~500 kHz, minimizing shoot-through risk and reducing switching losses compared to slower diodes - confirmed in Vishay's typical characteristics curves on page 3 of document 66744.

SIR403EDP-T1-GE3 Specifications

Product attributes: Attribute value

Manufacturer:: Vishay Siliconix

Series:: TrenchFET®

Package/Case:: PowerPAK® SO-8

Packaging:: Tape & Reel (TR)

Product Status:: Active

FET Type:: P-Channel

Technology:: MOSFET (Metal Oxide)

Drain to Source Voltage (Vdss):: 30 V

Current - Continuous Drain (Id) @ 25°C:: 40A (Tc)

Drive Voltage (Max Rds On, Min Rds On):: 4.5V, 10V

Rds On (Max) @ Id, Vgs:: 6.5mOhm @ 13A, 10V

Vgs(th) (Max) @ Id:: 2.8V @ 250µA

Gate Charge (Qg) (Max) @ Vgs:: 153 nC @ 10 V

Vgs (Max):: ±25V

Input Capacitance (Ciss) (Max) @ Vds:: 4620 pF @ 15 V

FET Feature:: -

Power Dissipation (Max):: 5W (Ta), 56.8W (Tc)

Operating Temperature:: -55°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: PowerPAK® SO-8

SIR403EDP-T1-GE3 FAQ

1.How can I place an order for SIR403EDP-T1-GE3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SIR403EDP-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SIR403EDP-T1-GE3 reliable?

The price and inventory of SIR403EDP-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIR403EDP-T1-GE3 is usually 5 days.

3.What payment methods are accepted for SIR403EDP-T1-GE3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIR403EDP-T1-GE3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SIR403EDP-T1-GE3?

SIR403EDP-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SIR403EDP-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SIR403EDP-T1-GE3?

For technical support, including SIR403EDP-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIR403EDP-T1-GE3 requirements.

6.How does Aetrix verify that SIR403EDP-T1-GE3 is sourced from the original manufacturer or authorized distributors?

All SIR403EDP-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIR403EDP-T1-GE3 meets industry standards.

7.What is the process for return or replacement of SIR403EDP-T1-GE3?

All SIR403EDP-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIR403EDP-T1-GE3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SIR403EDP-T1-GE3 part is unused and in its original packaging.

Return procedure for SIR403EDP-T1-GE3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-11 Comparator Circuit: Voltage Thresholds, Op-Amp Differences, LM393 and Practical Design

Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …