Vishay Siliconix SIR418DP-T1-GE3
- Part No.:
- SIR418DP-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SIR418DP-T1-GE3.pdf
- Description:
- MOSFET N-CH 40V 40A PPAK SO-8
- Quantity:
- Payment:

- Shipping:

Inventory:14,525
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Product details
Overview
SIR418DP-T1-GE3 from Vishay Siliconix is an N-channel 40-V PowerPAK® SO-8 MOSFET optimized for high-efficiency DC/DC conversion, with RDS(on) = 5.0 mΩ at VGS = 10 V, Qg = 24 nC (at 4.5 V), and 100 % UIS tested. It delivers 40 A continuous drain current at TC = 25 °C and operates in industrial power supplies where low conduction loss and fast switching are critical.
For engineers reviewing the SIR418DP-T1-GE3 datasheet, SIR418DP-T1-GE3 pinout, SIR418DP-T1-GE3 application, or SIR418DP-T1-GE3 equivalent, this page provides verified package mapping, thermal resistance data (RthJC = 2.1 °C/W), body diode recovery metrics (trr = 24 ns), and validated alternatives for synchronous buck and OR-ing designs.
Technical Context
This MOSFET employs a trench-gate silicon process optimized for low Qg/RDS(on) ratio, enabling high-frequency operation in synchronous rectification stages. Its gate threshold voltage (VGS(th) = 1.1–2.4 V) supports 4.5 V logic-level drive, and its 100 % Rg testing ensures consistent turn-on timing across production lots.
The PowerPAK® SO-8 package features exposed drain pads on the bottom side for direct thermal coupling to PCB copper, delivering DPAK-equivalent junction-to-case thermal resistance (2.1 °C/W) while maintaining SO-8 footprint compatibility. The device's 371 pF Coss and 141 pF Crss support stable operation under hard-switching conditions up to 1 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 40 V - Maximum blocking voltage for 12 V and 24 V input DC/DC stages |
| RDS(on) | 5.0 mΩ at VGS = 10 V - Enables ≤ 2 W conduction loss at 20 A in high-current POL converters |
| Qg | 24 nC at VGS = 4.5 V - Supports efficient 500 kHz–1 MHz switching with low gate drive power |
| ID (cont.) | 40 A at TC = 25 °C - Sustains full load in compact 1" × 1" FR4 board layouts without forced air |
| RthJC | 2.1 °C/W - Enables direct thermal path to heatsink or internal copper planes, matching DPAK performance |
| trr | 24 ns - Minimizes reverse recovery loss in synchronous buck high-side switching |
| VSD | 0.71 V at IS = 4 A - Low forward drop improves efficiency in OR-ing and hot-swap applications |
Pinout & Package
PowerPAK® SO-8 is a leadless surface-mount package with 8 terminals, identical in footprint and pinout to standard SO-8 but featuring exposed copper drain pads on the bottom for enhanced thermal conduction. Dimensions: 6.15 mm × 5.15 mm × 1.04 mm (L × W × H).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate | Control terminal; requires <2.4 V threshold to initiate conduction; Rg = 0.2–1.4 Ω ensures predictable switching speed |
| 2 (S) | Source | Reference node for gate drive; tied to power ground plane; carries full load current in low-side configuration |
| 3 (S) | Source | Second source connection; reduces source inductance and improves current sharing in high-di/dt applications |
| 4 (G) | Gate | Redundant gate terminal; electrically identical to Pin 1; used for Kelvin gate sensing or parallel drive routing |
| 5 (D) | Drain | Main power output node; connected to exposed bottom copper pad; handles 40 A continuous current |
| 6 (D) | Drain | Secondary drain terminal; shares current with Pin 5; lowers effective RDS(on) and thermal resistance |
| 7 (D) | Drain | Third drain terminal; part of multi-terminal drain structure enhancing thermal dissipation and current capacity |
| 8 (D) | Drain | Fourth drain terminal; completes symmetric drain layout; enables uniform current distribution across PCB copper area |
Key Features
| Feature | Design Value |
|---|---|
| Qg-optimized design | 24 nC at 4.5 V enables <20 ns rise time with 1 Ω gate resistor, reducing switching loss in 1 MHz converters |
| 100 % UIS tested | Guarantees ruggedness against inductive load transients up to 30 A avalanche current (IAS) |
| 100 % Rg tested | Ensures gate resistance between 0.2–1.4 Ω, critical for matched timing in paralleled MOSFET configurations |
| Halogen-free & RoHS compliant | Meets IEC 61249-2-21 and Directive 2002/95/EC for environmentally regulated industrial and telecom systems |
| Exposed drain thermal pad | Bottom-side copper enables 2.1 °C/W RthJC, allowing >39 W power dissipation at TC = 25 °C |
Applications
| Server VRM Output Stage | Industrial DC/DC Converter |
|---|---|
Use Scenario: High-current, multiphase buck converter supplying CPU core voltage (0.8–1.2 V) at up to 120 A per phase. IC Role / Device Role / Timing Role: Low-side synchronous rectifier; switched at 500 kHz–1 MHz with precise dead-time control to minimize shoot-through. Use Value: 5.0 mΩ RDS(on) limits conduction loss to <2.0 W at 20 A, while 24 ns trr prevents body diode cross-conduction loss during transition. | Use Scenario: 48 V-to-12 V isolated DC/DC module for factory automation controllers requiring high reliability over temperature. IC Role / Device Role / Timing Role: Secondary-side synchronous rectifier in LLC resonant topology; operated with adaptive gate timing to track zero-voltage switching points. Use Value: 100 % UIS testing ensures survival during line transients; 2.1 °C/W RthJC maintains TJ < 125 °C under full load on 2-oz copper PCB. |
| Hot-Swap OR-ing Circuit | Telecom Power Shelf |
Use Scenario: Redundant 12 V input OR-ing network in modular power system, where back-to-back MOSFETs prevent reverse current flow. IC Role / Device Role / Timing Role: Back-to-back configured N-channel MOSFET; body diode blocks reverse current until gate is actively driven. Use Value: 0.71 V VSD minimizes forward drop during startup; 35 A IS rating supports inrush current limiting without external diodes. | Use Scenario: Primary-side switch in 3 kW telecom rectifier shelf operating at 92 % efficiency with forced-air cooling. IC Role / Device Role / Timing Role: High-side switch in interleaved PFC stage; driven by isolated gate driver with 10 V gate bias. Use Value: 40 V VDS withstands 30 V bus ripple; 75 nC max Qg ensures <100 ns turn-off delay even at elevated temperature. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiR416DP-T1-GE3 | RDS(on) = 4.0 mΩ @ 10 V; Qg = 22 nC @ 4.5 V; same PowerPAK SO-8 package | Better conduction loss at high current; slightly lower gate charge enables faster switching | Select when optimizing for <10 mΩ target RDS(on) at 10 V drive and minimal gate drive loss |
| IRF7470PBF | SO-8 package; RDS(on) = 5.5 mΩ @ 10 V; Coss = 420 pF; no 100 % Rg test | Higher thermal resistance (RthJC = 3.5 °C/W); less suitable for high-power density layouts | Acceptable for cost-sensitive, lower-current (<15 A) applications where thermal margin is available |
Compared with SIR418DP-T1-GE3, SiR416DP-T1-GE3 offers lower RDS(on) and gate charge for improved efficiency at high frequency, while IRF7470PBF trades thermal performance and gate consistency for legacy SO-8 compatibility and lower unit cost.
Availability
SIR418DP-T1-GE3 is available at Aetrix Electronics and suitable for server VRMs, industrial DC/DC converters, hot-swap OR-ing circuits, and telecom power shelves requiring stable component supply, long-term lifecycle support, and traceable Pb-free sourcing.
Supply support for SIR418DP-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics for power management and signal conditioning.
The SiR418DP product line targets high-efficiency, high-density power conversion systems, with emphasis on low RDS(on), fast switching, and robust thermal packaging for server, telecom, and industrial applications.
FAQ
What is the maximum continuous drain current rating for SIR418DP-T1-GE3 at 70 °C case temperature?
The SIR418DP-T1-GE3 supports 40 A continuous drain current at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This rating is limited by package thermal capability rather than die saturation, and remains unchanged from its 25 °C rating due to the PowerPAK® SO-8's low RthJC (2.1 °C/W) and efficient heat spreading to PCB copper.
Does SIR418DP-T1-GE3 support 4.5 V gate drive in practical applications?
Yes, SIR418DP-T1-GE3 is fully characterized for 4.5 V gate drive: RDS(on) = 6.0 mΩ (max) at VGS = 4.5 V and ID = 15 A, and total gate charge is 24 nC (typ). Its VGS(th) range (1.1–2.4 V) ensures reliable enhancement-mode turn-on with standard 3.3 V or 5 V logic-level drivers, making it suitable for synchronous buck controllers without level-shifting.
How does the PowerPAK® SO-8 package of SIR418DP-T1-GE3 improve thermal performance versus standard SO-8?
The SIR418DP-T1-GE3's PowerPAK® SO-8 package achieves RthJC = 2.1 °C/W - matching DPAK performance - by exposing the drain pad on the bottom surface for direct thermal contact with PCB copper. In contrast, standard SO-8 packages exhibit RthJC ≈ 16 °C/W due to internal leadframe limitations. This allows SIR418DP-T1-GE3 to dissipate 39 W at TC = 25 °C, versus ~5 W for equivalent SO-8 devices.
Is SIR418DP-T1-GE3 suitable for avalanche energy handling in inductive switching applications?
Yes, SIR418DP-T1-GE3 is 100 % UIS (Unclamped Inductive Switching) tested per JEDEC JESD24-1, with rated single-pulse avalanche energy EAS = 45 mJ and avalanche current IAS = 30 A (L = 0.1 mH). This validation ensures robustness against transient voltage spikes in motor drives, solenoid controls, and flyback converters where inductive kickback occurs.
What is the body diode reverse recovery time (trr) of SIR418DP-T1-GE3, and why does it matter?
The SIR418DP-T1-GE3 has trr = 24 ns (typ) at IF = 10 A, dI/dt = 100 A/µs, and TJ = 25 °C. This fast recovery minimizes reverse recovery charge (Qrr = 15–30 nC), reducing switching loss and voltage overshoot during synchronous rectification transitions - especially critical in high-frequency (>500 kHz) buck converters where body diode conduction occurs during dead time.
SIR418DP-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 40 V
- Current - Continuous Drain (Id) @ 25°C:
- 40A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 5mOhm @ 20A, 10V
- Vgs(th) (Max) @ Id:
- 2.4V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 75 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 2410 pF @ 20 V
- FET Feature:
- -
- Power Dissipation (Max):
- 39W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SIR418DP-T1-GE3 FAQ
1.How can I place an order for SIR418DP-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIR418DP-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIR418DP-T1-GE3 reliable?
The price and inventory of SIR418DP-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIR418DP-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIR418DP-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIR418DP-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIR418DP-T1-GE3?
SIR418DP-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIR418DP-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIR418DP-T1-GE3?
For technical support, including SIR418DP-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIR418DP-T1-GE3 requirements.
6.How does Aetrix verify that SIR418DP-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIR418DP-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIR418DP-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIR418DP-T1-GE3?
All SIR418DP-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIR418DP-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIR418DP-T1-GE3 part is unused and in its original packaging.
Return procedure for SIR418DP-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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