Vishay Siliconix SIR474DP-T1-RE3
- Part No.:
- SIR474DP-T1-RE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SIR474DP-T1-RE3.pdf
- Description:
- MOSFET N-CH 30V 20A PPAK SO-8
- Quantity:
- Payment:

- Shipping:

Inventory:9,659
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SIR474DP-T1-RE3 from Vishay Siliconix is an N-channel 30 V (D-S) TrenchFET® power MOSFET in PowerPAK® SO-8 package, optimized for high-side synchronous rectifier operation in notebook CPU core power stages. It delivers RDS(on) = 9.5 mΩ at VGS = 10 V, 12.0 mΩ at VGS = 4.5 V, 20 A continuous drain current (TJ = 150 °C), and 8 nC total gate charge - enabling high-efficiency, space-constrained DC/DC conversion.
For engineers reviewing the SIR474DP-T1-RE3 datasheet, SIR474DP-T1-RE3 pinout, SIR474DP-T1-RE3 application, or SIR474DP-T1-RE3 equivalent, key selection criteria include its low-profile (1.07 mm) leadless PowerPAK SO-8 thermal performance, 100% Rg and UIS testing, and validated suitability for high-side switching in mobile computing VRMs where junction-to-case thermal resistance (RthJC = 3.5 °C/W typ.) and body diode recovery (trr = 14 ns typ.) directly impact efficiency and thermal margin.
Technical Context
This MOSFET employs trench-gate silicon technology to achieve low on-resistance with fast switching dynamics. Its gate charge profile (Qg = 8 nC typ. at VGS = 4.5 V) and low gate resistance (Rg = 0.3–2.6 Ω) support efficient gate drive in high-frequency synchronous buck converters. The device is characterized for stable operation across -55 °C to +150 °C junction temperature range.
Designed specifically for high-side configuration, it features a robust body diode (VSD = 0.76 V typ. at IS = 3 A, Qrr = 5 nC typ.) and avalanche-rated construction (EAS = 20 mJ). Thermal design leverages the exposed copper drain pad of the PowerPAK SO-8 for direct board heat sinking, achieving RthJC = 3.5 °C/W steady-state - comparable to DPAK performance in SO-8 footprint.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum drain-source blocking voltage for 12 V input VRM stages with margin against transients. |
| RDS(on) @ VGS = 10 V | 9.5 mΩ max - Enables <2 W conduction loss at 15 A in high-side switch position. |
| RDS(on) @ VGS = 4.5 V | 12.0 mΩ max - Ensures low on-resistance under typical 5 V gate drive from controller ICs. |
| Qg | 8 nC typ. - Reduces gate drive power and enables >1 MHz switching without excessive driver losses. |
| ID (continuous) | 20 A at TC = 25 °C - Supports high-current CPU core rails when mounted on thermally enhanced PCBs. |
| RthJC | 3.5 °C/W typ. - Allows direct thermal coupling to inner-layer copper planes, critical for notebook thermal envelope. |
| trr | 14 ns typ. - Minimizes reverse recovery loss during dead-time in synchronous rectification. |
Pinout & Package
Package: PowerPAK® SO-8 - leadless, 6.15 mm × 5.15 mm × 1.07 mm, with exposed copper drain pad on bottom surface for thermal and electrical connection. Compatible with standard SO-8 land patterns but requires extended drain copper area for optimal thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | Source (S) | Four parallel source terminals reduce source inductance and improve current sharing in high-di/dt applications. |
| 5 | Gate (G) | Single gate input with low Rg (0.3–2.6 Ω) for stable, low-noise turn-on/turn-off control. |
| 6, 7, 8 | Drain (D) | Three parallel drain terminals connected to large exposed copper pad - primary thermal path to PCB. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® silicon process | Delivers industry-leading RDS(on) × Qg figure-of-merit for high-frequency efficiency in VRMs. |
| PowerPAK® SO-8 package | 1.07 mm height enables ultra-thin notebook designs while providing DPAK-level thermal resistance (3.5 °C/W). |
| High-side synchronous rectifier optimization | Body diode trr = 14 ns and Qrr = 5 nC minimize shoot-through risk and recovery loss in buck topologies. |
| 100% Rg and UIS tested | Ensures gate robustness against transient overvoltage and ruggedness under unclamped inductive switching stress. |
| Lead (Pb)-free and halogen-free | Complies with RoHS Directive 2011/65/EU and JEDEC JS709C material definitions. |
Applications
| Notebook CPU Core VRM | Mobile GPU Power Stage |
|---|---|
Use Scenario: High-current, high-efficiency point-of-load regulation for Intel/AMD mobile processors with dynamic load steps up to 100 A/μs. IC Role / Device Role: High-side synchronous rectifier switch in multiphase buck converter delivering 0.8–1.5 V at up to 40 A per phase. Use Value: Low RDS(on) and fast trr reduce conduction and recovery losses, directly improving battery runtime by >2% at full load. |
Use Scenario: Compact, thermally constrained power delivery for discrete graphics processing units in ultrabooks and 2-in-1 devices. IC Role / Device Role: High-side FET in single-phase or dual-phase VRM supplying GPU core voltage with tight thermal budget (<65 °C board temp). Use Value: PowerPAK SO-8's 3.5 °C/W RthJC enables stable operation at 20 A without external heatsink, saving board area and BOM cost. |
| SSD Controller Power Rail | USB-C PD Sink Converter |
Use Scenario: Low-voltage, high-transient current supply for NVMe SSD controllers requiring fast load-step response and minimal voltage droop. IC Role / Device Role: High-side switch in 3.3 V or 1.8 V buck regulator with >500 kHz switching frequency. Use Value: 8 nC Qg and low Ciss (985 pF) allow clean, low-loss switching at high frequencies, preserving transient response and reducing output capacitance needs. |
Use Scenario: Secondary-side synchronous rectification in USB-C Power Delivery adapters delivering 5–20 V at up to 5 A. IC Role / Device Role: High-side FET in isolated flyback or active clamp forward topology operating at 100–300 kHz. Use Value: Optimized body diode characteristics (VSD = 0.76 V, trr = 14 ns) reduce reverse recovery loss and EMI, improving adapter efficiency and thermal compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel high-side MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiR476DP-T1-RE3 | Same PowerPAK SO-8 package; higher VDS = 40 V, RDS(on) = 11.5 mΩ @ 10 V (vs. 9.5 mΩ), Qg = 9.5 nC. | Better suited for 19 V input adapters or industrial 24 V systems where 30 V margin is insufficient. | Select SiR476DP-T1-RE3 only if system input voltage exceeds 15 V or transient protection headroom is critical. |
| IRF7478PBF | Standard SO-8 package; RDS(on) = 11.5 mΩ @ 10 V, RthJC = 16 °C/W (vs. 3.5 °C/W), no 100% UIS test. | Limited to lower-current, lower-frequency applications due to poor thermal performance and unverified avalanche ruggedness. | Use IRF7478PBF only in cost-sensitive, non-thermal-critical designs where PCB space allows larger thermal pads or forced air cooling. |
Compared with SiR474DP-T1-RE3, SiR476DP-T1-RE3 trades marginal on-resistance increase for wider input voltage capability, while IRF7478PBF sacrifices thermal performance and reliability validation for legacy SO-8 compatibility - making SIR474DP-T1-RE3 the optimal choice for thermally constrained, high-efficiency notebook CPU core VRMs.
Availability
SIR474DP-T1-RE3 is available at Aetrix Electronics and suitable for notebook CPU core VRMs, mobile GPU power stages, SSD controller rails, and USB-C PD sink converters requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production lots.
Supply support for SIR474DP-T1-RE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in power MOSFETs, diodes, and optoelectronics with emphasis on high-reliability, high-efficiency solutions for computing, automotive, and industrial markets.
The SIR474DP-T1-RE3 belongs to Vishay's TrenchFET® PowerPAK® SO-8 family, engineered specifically for high-density, high-efficiency DC/DC conversion in portable computing - prioritizing low RDS(on), fast switching, and superior thermal performance in minimal footprint.
FAQ
What is the maximum continuous drain current rating for SIR474DP-T1-RE3 at 70 °C case temperature?
The SIR474DP-T1-RE3 supports 20 A continuous drain current at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This rating assumes proper PCB thermal design with adequate copper area on the drain pad to maintain case temperature at or below 70 °C under full load conditions. Derating applies above this temperature per the current derating curve in the datasheet.
Is SIR474DP-T1-RE3 suitable for high-side synchronous rectification in a 500 kHz buck converter?
Yes, SIR474DP-T1-RE3 is explicitly optimized for high-side synchronous rectifier operation and supports 500 kHz switching with its 8 nC total gate charge (Qg) and low gate resistance (0.3–2.6 Ω). Measured turn-off delay (td(off) = 16–30 ns) and fall time (tf = 9–18 ns) at VGEN = 10 V confirm fast, controllable transitions essential for minimizing dead-time losses at this frequency.
Does SIR474DP-T1-RE3 have a qualified avalanche rating, and what is its EAS value?
Yes, SIR474DP-T1-RE3 is 100% UIS (unclamped inductive switching) tested per JEDEC JESD22-A115, with a rated single-pulse avalanche energy (EAS) of 20 mJ at TJ = 25 °C. This qualification ensures ruggedness against inductive energy spikes during hard-switching events in VRM applications, supporting reliable operation without external snubbers.
What is the recommended solder reflow profile for SIR474DP-T1-RE3?
The SIR474DP-T1-RE3 follows the Pb-free reflow profile defined in Vishay document 73257: peak temperature of 255 °C (+5/−0 °C) for 30 s, time above 217 °C between 60–150 s, ramp-up rate ≤3 °C/s, and ramp-down rate ≤6 °C/s. Manual soldering with an iron is not recommended due to its leadless PowerPAK® SO-8 construction and exposed copper drain pad.
How does the PowerPAK® SO-8 package of SIR474DP-T1-RE3 improve thermal performance versus standard SO-8?
The SIR474DP-T1-RE3's PowerPAK® SO-8 achieves RthJC = 3.5 °C/W (typ.), matching DPAK performance - a 4.6× improvement over standard SO-8's 16 °C/W. This is enabled by the exposed copper drain pad directly bonded to PCB copper, eliminating leadframe thermal bottlenecks. In practice, this reduces junction temperature rise by ~40 °C at 2.7 W dissipation compared to standard SO-8 equivalents.
SIR474DP-T1-RE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 20A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 9.5mOhm @ 10A, 10V
- Vgs(th) (Max) @ Id:
- 2.2V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 27 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 985 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 29.8W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SIR474DP-T1-RE3 FAQ
1.How can I place an order for SIR474DP-T1-RE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIR474DP-T1-RE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIR474DP-T1-RE3 reliable?
The price and inventory of SIR474DP-T1-RE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIR474DP-T1-RE3 is usually 5 days.
3.What payment methods are accepted for SIR474DP-T1-RE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIR474DP-T1-RE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIR474DP-T1-RE3?
SIR474DP-T1-RE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIR474DP-T1-RE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIR474DP-T1-RE3?
For technical support, including SIR474DP-T1-RE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIR474DP-T1-RE3 requirements.
6.How does Aetrix verify that SIR474DP-T1-RE3 is sourced from the original manufacturer or authorized distributors?
All SIR474DP-T1-RE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIR474DP-T1-RE3 meets industry standards.
7.What is the process for return or replacement of SIR474DP-T1-RE3?
All SIR474DP-T1-RE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIR474DP-T1-RE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIR474DP-T1-RE3 part is unused and in its original packaging.
Return procedure for SIR474DP-T1-RE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SIR474DP-T1-RE3 Tags

-
BSZ180P03NS3EGATMA1
Infineon Technologies

-
SIRA14DP-T1-GE3
Vishay Siliconix

-
AO4419
Alpha & Omega Semiconductor Inc.

-
SISA14BDN-T1-GE3
Vishay Siliconix

-
PSMN9R5-30YLC,115
Nexperia USA Inc.

-
BUK9Y21-40E,115
Nexperia USA Inc.

-
RTQ035N03HZGTR
Rohm Semiconductor

-
FDMS7680
onsemi

-
RQ3E180BNTB
Rohm Semiconductor

-
STL6N2VH5
STMicroelectronics

-
DMPH4029LFGQ-7
Diodes Incorporated

-
DMT6015LSS-13
Diodes Incorporated
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

