Vishay Siliconix SIR484DP-T1-GE3
- Part No.:
- SIR484DP-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SIR484DP-T1-GE3.pdf
- Description:
- MOSFET N-CH 20V 20A PPAK SO-8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SIR484DP-T1-GE3 from Vishay Siliconix is an N-channel 20-V TrenchFET® Power MOSFET in PowerPAK® SO-8 package, optimized for high-side synchronous rectifier operation in notebook CPU core power delivery. It delivers RDS(on) = 8.3 mΩ at VGS = 10 V, 7.1 nC total gate charge, and 20 A continuous drain current (TC = 25 °C), enabling high-efficiency DC-DC conversion in space-constrained POL applications.
For engineers reviewing the SIR484DP-T1-GE3 datasheet, SIR484DP-T1-GE3 pinout, SIR484DP-T1-GE3 application, or SIR484DP-T1-GE3 equivalent, key selection criteria include its low thermal resistance (RthJC = 3.5 °C/W), halogen-free/lead-free compliance, 100 % Rg and UIS tested reliability, and compatibility with standard SO-8 land patterns while delivering DPAK-level thermal performance.
Technical Context
This MOSFET employs trench-gate silicon technology to achieve low on-resistance and fast switching dynamics. Its gate threshold voltage (VGS(th) = 1.0–2.5 V) supports logic-level drive, and its dynamic parameters-including Ciss = 830 pF, Coss = 280 pF, and Qgd = 1.6 nC-enable efficient high-frequency synchronous rectification.
The device operates with a maximum VDS of 20 V and is rated for junction temperatures from –55 °C to +150 °C. Its PowerPAK® SO-8 package features exposed copper drain pads for direct thermal conduction to PCB copper, achieving RthJA = 27 °C/W (typ.) on FR4 and RthJC = 3.5 °C/W (typ.), critical for thermally dense CPU core VRMs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 20 V - Maximum drain-source blocking voltage compatible with 19-V input rails in notebook CPU core converters. |
| RDS(on) | 8.3 mΩ @ VGS = 10 V - Enables <1.7 W conduction loss at 20 A, reducing heat generation in high-current POL stages. |
| Qg | 7.1 nC @ VGS = 4.5 V - Low gate charge minimizes driver power and switching losses in 300–1000 kHz synchronous buck topologies. |
| ID (cont) | 20 A @ TC = 25 °C - Package-limited current rating suitable for high-phase-count multiphase VRMs powering modern mobile CPUs. |
| RthJC | 3.5 °C/W (typ.) - Enables direct thermal coupling to PCB copper, allowing die temperature rise ≤3.5 °C per watt dissipated at the case. |
| VGS(th) | 1.0–2.5 V - Ensures reliable turn-on with standard 3.3 V or 5 V gate drivers without level-shifting circuitry. |
| Body diode VSD | 0.8–1.2 V @ IS = 10 A - Low forward voltage reduces reverse-recovery losses during dead-time conduction in synchronous rectifiers. |
Pinout & Package
PowerPAK® SO-8 is a leadless surface-mount package with same footprint and pinout as standard SO-8, featuring exposed copper drain pads on the bottom for enhanced thermal transfer. Height is 1.07 mm (max), enabling ultra-thin notebook designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 6, 7, 8 | Drain (D) | Seven parallel drain terminals connected to internal die and bottom-side exposed copper pad - primary thermal and current path to PCB ground plane. |
| 5 | Gate (G) | Single gate input controlling channel conduction - requires low-inductance routing to minimize ringing and EMI in high-dI/dt switching. |
| Source (S) | Source (S) | Terminals 1 and 2 are source pins - tied internally to source metallization and used for Kelvin sensing or low-impedance return path in high-accuracy current monitoring. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® technology | Enables 8.3 mΩ RDS(on) at 20 V rating - achieves higher current density than planar MOSFETs in same footprint. |
| Optimized for high-side synchronous rectifier | Low Qgd/Qg ratio (1.6/7.1 ≈ 0.23) improves hard-switching robustness and reduces Miller-induced shoot-through risk. |
| 100 % Rg tested | Guarantees gate resistance ≤3.8 Ω - ensures predictable turn-on/turn-off timing and driver stage stability. |
| 100 % UIS tested | Validated avalanche energy rating of 24 mJ - provides ruggedness against inductive switching transients in unregulated POL outputs. |
| Halogen-free & Pb-free | Meets IPC-J-STD-609 Class 1 and JEDEC JS709B requirements - compliant with RoHS and green manufacturing standards. |
Applications
| Notebook CPU Core High-Side Switch | POL DC-DC Converter |
|---|---|
Use Scenario: Primary high-side switch in multiphase buck converter supplying dynamic load currents up to 100 A to Intel/AMD mobile processors. IC Role / Device Role / Timing Role: High-side synchronous rectifier MOSFET operating at 300–600 kHz with precise gate timing controlled by VRM controller. Use Value: 8.3 mΩ RDS(on) and 7.1 nC Qg reduce both conduction and switching losses, improving full-load efficiency by ≥1.2 % versus legacy SO-8 MOSFETs. | Use Scenario: Point-of-load regulator on motherboard or GPU module delivering tightly regulated 0.8–1.5 V to ASICs or memory subsystems. IC Role / Device Role / Timing Role: High-current, low-voltage power switch handling peak currents >20 A with minimal thermal rise on compact PCB area. Use Value: RthJC = 3.5 °C/W enables direct thermal coupling to inner-layer copper, limiting junction temperature rise to <70 °C at 20 A continuous - avoids derating in thermally constrained zones. |
| High-Efficiency Laptop VRM | Thin-Profile Mobile Adapter |
Use Scenario: Integrated voltage regulator module (VRM) embedded in ultrabook chassis with strict height budget (<1.2 mm). IC Role / Device Role / Timing Role: High-side power switch in integrated DrMOS or discrete dual-phase controller architecture. Use Value: 1.07 mm profile and PowerPAK® SO-8 footprint allow drop-in replacement of taller SO-8 devices without redesigning board stack-up or component keep-out zones. | Use Scenario: Secondary-side synchronous rectifier in compact AC-DC adapter for 15–45 W laptop chargers. IC Role / Device Role / Timing Role: Low-VDS MOSFET replacing Schottky diode to reduce forward voltage drop and improve light-load efficiency. Use Value: Body diode VSD = 0.8–1.2 V and trr = 15–30 ns enable clean commutation with minimal reverse recovery loss - increases adapter efficiency by 0.8–1.5 % at 20 % load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel 20-V power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiR482DP-T1-GE3 | RDS(on) = 9.5 mΩ @ 4.5 V (vs. 11.5 mΩ for SIR484DP); Qg = 6.2 nC (vs. 7.1 nC); same PowerPAK® SO-8 package. | Slightly lower conduction loss at mid-VGS, but marginally reduced current rating (19 A vs. 20 A). | Preferred where gate drive voltage is stable at 4.5 V and lowest possible Qg dominates over absolute RDS(on) minimization. |
| SiR472DP-T1-GE3 | RDS(on) = 7.2 mΩ @ 10 V (vs. 8.3 mΩ); Qg = 8.5 nC (vs. 7.1 nC); identical thermal specs and package. | Better conduction efficiency at full 10 V drive, but higher switching loss due to +20 % Qg. | Selected when system uses 10 V gate drivers and thermal headroom allows higher Qg-induced losses. |
Compared with SIR484DP-T1-GE3, SiR482DP-T1-GE3 trades marginal RDS(on) increase for lower gate charge in 4.5 V drive systems, while SiR472DP-T1-GE3 prioritizes lowest on-resistance at 10 V at the expense of higher switching loss - enabling optimization for either drive voltage or thermal envelope constraints.
Availability
SIR484DP-T1-GE3 is available at Aetrix Electronics and suitable for notebook CPU core VRMs, POL DC-DC converters, and high-efficiency laptop adapter designs requiring stable component supply, consistent parametric performance across production lots, and long-term lifecycle support.
Supply support for SIR484DP-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency, thermal management, and reliability.
The SiR484DP product line is part of Vishay's TrenchFET® PowerPAK® SO-8 family, engineered specifically for high-current, high-frequency synchronous rectification in space- and thermally-constrained computing and portable power applications.
FAQ
What is the maximum continuous drain current rating for SIR484DP-T1-GE3?
The SIR484DP-T1-GE3 is rated for 20 A continuous drain current at TC = 25 °C, limited by package thermal capacity. At TC = 70 °C, the rating remains 20 A, while ambient-limited operation drops to 13.7 A at TA = 70 °C per the datasheet's derating curve. This reflects its package-limited design rather than silicon-limited capability.
Does SIR484DP-T1-GE3 support logic-level gate drive?
Yes, SIR484DP-T1-GE3 has a gate threshold voltage range of 1.0–2.5 V and delivers RDS(on) = 11.5 mΩ at VGS = 4.5 V, making it fully compatible with 3.3 V and 4.5 V logic-level gate drivers without requiring external level shifters - essential for integration into compact VRM controllers.
What is the thermal resistance from junction to case for SIR484DP-T1-GE3?
The SIR484DP-T1-GE3 has a typical junction-to-case (drain) thermal resistance RthJC of 3.5 °C/W, with a maximum of 4.2 °C/W. This low value is enabled by the PowerPAK® SO-8's exposed copper drain pad, which provides a direct thermal path from die to PCB copper, critical for maintaining safe junction temperatures under high-current POL loads.
Is SIR484DP-T1-GE3 pin-compatible with standard SO-8 packages?
Yes, SIR484DP-T1-GE3 uses the PowerPAK® SO-8 package, which maintains identical footprint, pin count, and pinout (G, S, D configuration) as the industry-standard SO-8. It can be mounted on existing SO-8 land patterns, though optimal thermal performance requires extending the drain pad copper area per Vishay Application Note AN821.
What does "100 % UIS tested" mean for SIR484DP-T1-GE3?
"100 % UIS tested" means every SIR484DP-T1-GE3 unit undergoes individual Unclamped Inductive Switching stress testing to validate its 24 mJ avalanche energy rating (EAS). This ensures robustness against voltage spikes caused by parasitic inductance during turn-off - a critical reliability requirement in high-dI/dt CPU core power stages.
SIR484DP-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 20A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 8.3mOhm @ 17.2A, 10V
- Vgs(th) (Max) @ Id:
- 2.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 23 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 830 pF @ 10 V
- FET Feature:
- -
- Power Dissipation (Max):
- 3.9W (Ta), 29.8W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SIR484DP-T1-GE3 FAQ
1.How can I place an order for SIR484DP-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIR484DP-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIR484DP-T1-GE3 reliable?
The price and inventory of SIR484DP-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIR484DP-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIR484DP-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIR484DP-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIR484DP-T1-GE3?
SIR484DP-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIR484DP-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIR484DP-T1-GE3?
For technical support, including SIR484DP-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIR484DP-T1-GE3 requirements.
6.How does Aetrix verify that SIR484DP-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIR484DP-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIR484DP-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIR484DP-T1-GE3?
All SIR484DP-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIR484DP-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIR484DP-T1-GE3 part is unused and in its original packaging.
Return procedure for SIR484DP-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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