Vishay Siliconix SIR588DP-T1-RE3
- Part No.:
- SIR588DP-T1-RE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SIR588DP-T1-RE3.pdf
- Description:
- N-CHANNEL 80 V (D-S) MOSFET POWE
- Quantity:
- Payment:

- Shipping:

Inventory:5,930
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Product details
Overview
SIR588DP-T1-RE3 from Vishay Siliconix is an N-channel 80 V (D-S) TrenchFET® Gen V power MOSFET in PowerPAK® SO-8 package, delivering RDS(on) = 8.0 mΩ at VGS = 10 V, Qg = 14.2 nC (typ.), and continuous drain current ID = 59.5 A (TC = 25 °C), optimized for high-efficiency synchronous rectification and primary-side switching in DC/DC converters.
For engineers reviewing the SIR588DP-T1-RE3 datasheet, SIR588DP-T1-RE3 pinout, SIR588DP-T1-RE3 application, or SIR588DP-T1-RE3 equivalent, key selection criteria include its low RDS(on) × Qg and RDS(on) × Qoss figures-of-merit, 100% Rg and UIS testing, and thermal performance with RthJC = 1.7 °C/W (typ.) for high-power density designs.
Technical Context
This MOSFET employs TrenchFET® Gen V silicon technology to achieve ultra-low conduction and switching losses. Its gate charge profile-Qg = 14.2 nC (VGS = 7.5 V), Qgd = 2.1 nC, and Qoss = 40 pC-enables fast, efficient hard-switching in high-frequency topologies. The device features a robust body diode with trr = 36 ns (typ.) and Qrr = 32 nC (typ.) at IF = 10 A, supporting ZVS and soft-recovery operation.
Thermally, it uses a leadless PowerPAK® SO-8 package with exposed drain copper on the bottom side, enabling direct thermal coupling to PCB copper. Its RthJC = 1.7 °C/W (typ.) and RthJA = 21 °C/W (t ≤ 10 s) support high-current operation under constrained thermal conditions, while the 100% UIS-tested construction ensures ruggedness in inductive load switching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 80 V - Maximum blocking voltage for primary-side switch or OR-ing applications up to 48 V bus systems with margin. |
| RDS(on) max. @ VGS = 10 V | 8.0 mΩ - Enables <1 W conduction loss at 35 A, critical for high-current DC/DC output stages. |
| Qg typ. @ VGS = 7.5 V | 14.2 nC - Low gate drive energy reduces driver IC loading and switching loss in 300–1000 kHz converters. |
| ID continuous @ TC = 25 °C | 59.5 A - Supports >500 W power delivery with appropriate heatsinking on 1" × 1" FR4 board. |
| RthJC typical | 1.7 °C/W - Allows junction temperature rise of only ~100 °C at 60 W dissipation, enabling compact thermal design. |
| VGS(th) | 2–4 V - Compatible with standard 5 V and 3.3 V logic-level gate drivers without level shifting. |
| Ciss | 1380 pF - Predictable input capacitance simplifies gate drive loop stability analysis in high-speed designs. |
Pinout & Package
Package: PowerPAK® SO-8 (leadless, exposed drain pad), dimensions 5.15 mm × 6.15 mm × 1.04 mm (L × W × H), RoHS-compliant and halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | Source (S) | Four parallel source terminals reduce source inductance and improve current sharing in high-di/dt switching. |
| 5 | Gate (G) | Single gate input with Rg = 0.4–1.8 Ω (typ./max); low gate resistance supports fast turn-on/turn-off control. |
| 6, 7, 8, Bottom Pad | Drain (D) | Multi-terminal drain connection plus large exposed copper pad provides low-inductance, high-current path and primary thermal interface to PCB. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® Gen V silicon | Delivers best-in-class RDS(on) × Qg FOM (≈113 mΩ·nC), reducing total switching + conduction loss in high-frequency SMPS. |
| 100% Rg and UIS tested | Ensures gate robustness against transient overvoltage and avalanche energy handling up to EAS = 31.25 mJ. |
| Optimized RDS(on) × Qoss FOM | Minimizes capacitive turn-off loss and improves light-load efficiency in resonant and quasi-resonant converters. |
| Low VSD body diode | VSD = 0.78 V (typ.) at IS = 5 A enables efficient synchronous rectification without external Schottky replacement. |
| Exposed drain thermal pad | Enables direct PCB copper thermal spreading, achieving RthJA = 21 °C/W (t ≤ 10 s) on minimal 1" × 1" FR4 layout. |
Applications
| Synchronous Rectification | Primary-Side Switch |
|---|---|
Use Scenario: Secondary-side switching in isolated DC/DC converters (e.g., LLC, phase-shifted full-bridge) operating at 200–500 kHz. IC Role / Device Role: Low-loss synchronous rectifier replacing Schottky diodes to reduce conduction loss and improve efficiency above 12 V output. Use Value: RDS(on) = 8.0 mΩ and low Qrr = 32 nC enable >1.5% efficiency gain vs. 40 V Schottky at 20 A load, with reduced thermal stress. |
Use Scenario: High-current primary switch in 48 V input telecom or server PSUs using hard-switched or ZVS topologies. IC Role / Device Role: Main power switch handling up to 59.5 A continuous drain current with 80 V VDS rating for 48 V nominal bus. Use Value: Low RDS(on) × Qg minimizes combined switching and conduction loss, supporting >95% efficiency at 500 W output. |
| OR-ing / Hot Swap | Battery Management System |
Use Scenario: Redundant power rail OR-ing in industrial PLCs or datacom equipment with 12–48 V inputs. IC Role / Device Role: Back-to-back configured N-channel MOSFET providing low-forward-drop, bidirectional current control with reverse polarity protection. Use Value: VGS(th) = 2–4 V allows simple gate drive from rail monitor ICs; low RDS(on) limits voltage drop to <0.5 V at 30 A. |
Use Scenario: Cell-balancing or pack protection switch in 16–24 cell Li-ion battery packs (up to 80 V system). IC Role / Device Role: High-side or low-side protection switch controlling charge/discharge paths with overcurrent and short-circuit response. Use Value: 100% UIS tested and EAS = 31.25 mJ ensure survivability during fault events; low RDS(on) reduces self-heating during extended discharge. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiR626DP-T1-RE3 | RDS(on) = 5.0 mΩ @ 10 V, VDS = 60 V, Qg = 20.5 nC - lower RDS(on) but reduced voltage rating. | Best suited for ≤48 V primary switches where lower conduction loss outweighs voltage margin. | Select when system VIN ≤ 42 V and RDS(on) reduction is prioritized over 80 V headroom. |
| IRF7470PBF | RDS(on) = 9.0 mΩ @ 10 V, VDS = 80 V, Qg = 24.5 nC, TO-252 package - same voltage rating but higher Qg and larger footprint. | Preferred where through-hole or larger thermal mass is acceptable and gate drive capability is ample. | Choose when PCB space permits DPAK and thermal requirements allow higher RthJA (~62 °C/W). |
Compared with SiR626DP-T1-RE3, SIR588DP-T1-RE3 offers superior voltage margin for 48 V systems with transients, while versus IRF7470PBF it delivers significantly better high-frequency efficiency and smaller board area via PowerPAK® SO-8 packaging.
Availability
SIR588DP-T1-RE3 is available at Aetrix Electronics and suitable for synchronous rectification, primary-side switching, and OR-ing applications requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.
Supply support for SIR588DP-T1-RE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency, reliability, and miniaturization.
The PowerPAK® SO-8 TrenchFET® Gen V series-including SIR588DP-T1-RE3-is engineered for high-density, high-efficiency power conversion in telecom, computing, and industrial power supplies.
FAQ
What is the maximum continuous drain current rating for SIR588DP-T1-RE3 at case temperature 70 °C?
The SIR588DP-T1-RE3 supports a continuous drain current of 47.6 A at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This derated value reflects thermal limitations under sustained high-temperature operation and must be validated against actual board layout and heatsinking in the target application. The SIR588DP-T1-RE3 maintains RDS(on) = 8.0 mΩ at VGS = 10 V across this range, ensuring predictable conduction loss.
Does SIR588DP-T1-RE3 require a gate resistor for reliable switching in a 500 kHz DC/DC converter?
Yes, a gate resistor is recommended for controlled turn-on/turn-off to manage EMI and prevent ringing. With Qg = 14.2 nC (VGS = 7.5 V) and Rg = 0.4–1.8 Ω (typ./max), a 5–10 Ω external resistor typically achieves optimal dV/dt and di/dt control at 500 kHz. The SIR588DP-T1-RE3's low intrinsic Rg makes it responsive to moderate gate drive strength, avoiding excessive overshoot or shoot-through risk.
Can SIR588DP-T1-RE3 be used in a back-to-back configuration for bidirectional OR-ing?
Yes, the SIR588DP-T1-RE3 is suitable for back-to-back N-channel configurations in OR-ing and hot-swap circuits. Its VGS(th) = 2–4 V enables reliable enhancement-mode turn-on with standard gate drivers, and its 100% UIS-tested construction withstands reverse-bias avalanche during fault transients. When used in such configurations, the SIR588DP-T1-RE3 leverages its low RDS(on) to minimize forward voltage drop and power loss in both directions.
What is the thermal resistance from junction to ambient (RthJA) for SIR588DP-T1-RE3 on a standard PCB?
The SIR588DP-T1-RE3 has a typical RthJA of 21 °C/W for t ≤ 10 s when mounted on a 1" × 1" FR4 board per the datasheet test condition. This value assumes surface mounting with no additional heatsink; steady-state RthJA is not characterized due to package limitations. For thermal design, use RthJC = 1.7 °C/W (typ.) with measured case temperature, as the SIR588DP-T1-RE3's exposed drain pad dominates heat transfer to the PCB.
Is SIR588DP-T1-RE3 suitable for use in automotive-grade power modules?
The SIR588DP-T1-RE3 is not AEC-Q101 qualified and is intended for industrial, computing, and telecom applications-not automotive. While its operating junction temperature range (−55 °C to +150 °C) meets automotive ambient requirements, it lacks the required qualification testing, failure analysis reporting, and PPAP documentation. For automotive use, consider Vishay's AEC-Q101-qualified alternatives like SQJQ480E or SIJQ480E instead of the SIR588DP-T1-RE3.
SIR588DP-T1-RE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET® Gen V
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 80 V
- Current - Continuous Drain (Id) @ 25°C:
- 17.2A (Ta), 59.5A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 7.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 8mOhm @ 10A, 10V
- Vgs(th) (Max) @ Id:
- 4V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 28.5 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1380 pF @ 40 V
- FET Feature:
- -
- Power Dissipation (Max):
- 5W (Ta), 59.5W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SIR588DP-T1-RE3 FAQ
1.How can I place an order for SIR588DP-T1-RE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIR588DP-T1-RE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIR588DP-T1-RE3 reliable?
The price and inventory of SIR588DP-T1-RE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIR588DP-T1-RE3 is usually 5 days.
3.What payment methods are accepted for SIR588DP-T1-RE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIR588DP-T1-RE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIR588DP-T1-RE3?
SIR588DP-T1-RE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIR588DP-T1-RE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIR588DP-T1-RE3?
For technical support, including SIR588DP-T1-RE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIR588DP-T1-RE3 requirements.
6.How does Aetrix verify that SIR588DP-T1-RE3 is sourced from the original manufacturer or authorized distributors?
All SIR588DP-T1-RE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIR588DP-T1-RE3 meets industry standards.
7.What is the process for return or replacement of SIR588DP-T1-RE3?
All SIR588DP-T1-RE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIR588DP-T1-RE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIR588DP-T1-RE3 part is unused and in its original packaging.
Return procedure for SIR588DP-T1-RE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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