Vishay Siliconix SIR866DP-T1-GE3
- Part No.:
- SIR866DP-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® SO-8
- Datasheet:
-
SIR866DP-T1-GE3.pdf
- Description:
- MOSFET N-CH 20V 60A PPAK SO-8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SIR866DP-T1-GE3 from Vishay Siliconix is an N-channel 20-V TrenchFET® Gen III Power MOSFET in PowerPAK SO-8 package, delivering 60 A continuous drain current at TC = 25 °C, RDS(on) of 1.9 mΩ at VGS = 10 V and 2.55 mΩ at VGS = 4.5 V, with 35.3 nC total gate charge - optimized for low-side DC-to-DC conversion and OR-ing applications in telecom power systems.
For engineers reviewing the SIR866DP-T1-GE3 datasheet, SIR866DP-T1-GE3 pinout, SIR866DP-T1-GE3 application, or SIR866DP-T1-GE3 equivalent, key selection criteria include its 20-V VDS rating, ultra-low on-resistance, PWM-optimized Qgd/Rg, 100 % UIS testing, and lead-free/halogen-free PowerPAK SO-8 packaging compatible with standard SO-8 footprints.
Technical Context
This MOSFET employs TrenchFET® Gen III silicon technology to achieve low RDS(on) and high current density within a thermally enhanced PowerPAK SO-8 package. Its gate charge profile (Qg = 35.3 nC at VGS = 4.5 V, Qgd = 9.5 nC) and low gate resistance (Rg = 0.2–1.9 Ω) support efficient high-frequency switching in synchronous rectification and load-switching topologies.
The device features fully rated avalanche capability (EAS = 80 mJ, IAS = 40 A), 100 % UIS tested, and operates across –55 °C to +150 °C junction temperature range. Thermal performance is characterized by RthJC = 1.0–1.5 °C/W (junction-to-case) and RthJA = 18–23 °C/W (junction-to-ambient, t ≤ 10 s), enabled by exposed-drain thermal pad construction.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 20 V - Maximum drain-source blocking voltage; suitable for 12-V input rail systems with margin. |
| RDS(on) | 1.9 mΩ @ VGS = 10 V - Enables <1.2 W conduction loss at 60 A; critical for high-efficiency low-side switch operation. |
| ID (continuous) | 60 A @ TC = 25 °C - Package-limited current handling; requires adequate PCB copper for thermal management. |
| Qg | 35.3 nC @ VGS = 4.5 V - Low gate drive energy supports efficient 5-V gate control in PWM circuits. |
| Qgd | 9.5 nC - Minimizes Miller plateau duration, improving switching speed and reducing overlap losses. |
| RthJC | 1.0–1.5 °C/W - Enables direct heat transfer from die to PCB copper; matches DPAK-level thermal performance. |
| VGS(th) | 1.2–2.3 V - Ensures robust turn-on with 3.3-V or 5-V logic-level gate drivers. |
Pinout & Package
Package: PowerPAK SO-8 (leadless, exposed-drain thermal pad), 6.15 mm × 5.15 mm footprint, identical pinout and land pattern compatibility with standard SO-8 - enables drop-in replacement without PCB redesign.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G) | Gate | Control terminal; low Rg (0.2–1.9 Ω) minimizes gate drive loop inductance sensitivity. |
| 2 (S) | Source | Reference node for gate drive; tied to power ground plane in low-side configurations. |
| 3 (S) | Source | Dual-source connection improves current sharing and reduces source inductance in high-di/dt paths. |
| 4 (S) | Source | Third source terminal enhances thermal and electrical connection to PCB ground plane. |
| 5 (D) | Drain | Main power output node; exposed bottom-side copper pad provides primary thermal path to PCB. |
| 6 (D) | Drain | Second drain terminal increases current-carrying capacity and reduces package inductance. |
| 7 (D) | Drain | Third drain terminal supports high-current routing and improves thermal spreading under drain pad. |
| 8 (D) | Drain | Fourth drain terminal completes symmetric drain layout for balanced current distribution and EMI reduction. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® Gen III silicon | Delivers 1.9 mΩ RDS(on) at 10 V in SO-8 footprint - 3× lower on-resistance than prior-gen SO-8 MOSFETs. |
| PWM-optimized Qgd and Rg | Qgd = 9.5 nC and Rg = 0.2–1.9 Ω enable fast, controllable switching with minimal shoot-through risk in synchronous buck stages. |
| 100 % UIS tested | Guarantees ruggedness against unclamped inductive switching events common in DC-DC converter freewheeling phases. |
| PowerPAK SO-8 package | Exposes drain pad for direct thermal coupling to PCB; achieves RthJC = 1.0 °C/W - equivalent to DPAK, not standard SO-8. |
| Halogen-free & RoHS-compliant | Meets IPC-4101D/21 and JEDEC J-STD-020 reflow standards; peak solder temperature up to 260 °C. |
Applications
| Telecom Power Supply | Server VRM Low-Side Switch |
|---|---|
Use Scenario: 48-V to 12-V intermediate bus converter in fixed telecom infrastructure with strict efficiency and reliability requirements. IC Role / Device Role / Timing Role: Low-side synchronous rectifier in multiphase buck converter; switches at 300–600 kHz with 5-V gate drive. Use Value: 1.9-mΩ RDS(on) reduces conduction loss by >40 % vs. legacy SO-8 MOSFETs, enabling >95 % efficiency at full load. | Use Scenario: Output stage of server voltage regulator module supplying CPU core power with dynamic load steps up to 200 A/µs. IC Role / Device Role / Timing Role: Low-side power switch in 3+1 phase buck topology; handles 60-A continuous per phase with tight thermal constraints. Use Value: PowerPAK SO-8's 1.0 °C/W RthJC allows stable 125 °C junction operation on 4-layer FR4 board without heatsink. |
| OR-ing Controller Circuit | Industrial 24-V DC Power Distribution |
Use Scenario: Redundant 12-V power rail combining using ideal diode configuration in network equipment with hot-swap capability. IC Role / Device Role / Timing Role: Back-to-back configured N-channel MOSFET acting as low-loss forward conduction path; controlled by dedicated OR-ing IC. Use Value: 2.55-mΩ RDS(on) at 4.5 V ensures <150 mV forward drop at 60 A, minimizing power loss and thermal rise during fault conditions. | Use Scenario: High-current load switch in programmable logic controller (PLC) backplane powering multiple I/O modules. IC Role / Device Role / Timing Role: Solid-state replacement for mechanical relay; switched via microcontroller GPIO with 5-V level-shifter. Use Value: 100 % UIS tested rating withstands inductive kickback from solenoid loads, eliminating need for external snubbers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel 20-V power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SiR872DP-T1-GE3 | Same PowerPAK SO-8 package; higher RDS(on) = 2.3 mΩ @ 10 V; Qg = 42.5 nC @ 4.5 V. | Lower current rating (50 A vs. 60 A); suited for space-constrained designs where marginally higher loss is acceptable. | Select when thermal budget allows 0.4-mΩ higher RDS(on) and gate drive capability supports +20 % Qg. |
| IRLHS6342TRPBF | SO-8 package; RDS(on) = 2.2 mΩ @ 4.5 V; Qg = 34 nC; no 100 % UIS test specified. | Standard SO-8 (not PowerPAK); RthJC = 16 °C/W - requires larger PCB copper area to match thermal performance. | Choose only if existing SO-8 land pattern must be reused without thermal pad enhancement; verify UIS robustness separately. |
Compared with SIR866DP-T1-GE3, SiR872DP-T1-GE3 trades 0.4-mΩ higher on-resistance for tighter gate charge distribution, while IRLHS6342TRPBF sacrifices thermal performance and avalanche ruggedness for broader distributor availability - making SIR866DP-T1-GE3 optimal for high-reliability, high-efficiency telecom and server applications.
Availability
SIR866DP-T1-GE3 is available at Aetrix Electronics and suitable for telecom power supplies, server VRMs, OR-ing circuits, and industrial 24-V DC distribution systems requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production lots.
Supply support for SIR866DP-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with emphasis on power efficiency, ruggedness, and miniaturization.
The SiR866DP product line belongs to Vishay's TrenchFET® Gen III PowerPAK SO-8 family, engineered specifically for high-current, high-frequency switching in space-constrained telecom, computing, and industrial power systems.
FAQ
What is the maximum continuous drain current rating for SIR866DP-T1-GE3 at 70 °C case temperature?
The SIR866DP-T1-GE3 is rated for 60 A continuous drain current at TC = 70 °C, as confirmed in the Absolute Maximum Ratings table (Document Number: 68751, Rev. A). This rating is package-limited and assumes proper PCB thermal design with adequate copper area under the exposed drain pad to maintain junction temperature ≤ 150 °C.
Does SIR866DP-T1-GE3 support 3.3-V gate drive in logic-level applications?
Yes, SIR866DP-T1-GE3 supports 3.3-V gate drive: its gate threshold voltage VGS(th) ranges from 1.2 V to 2.3 V, and it delivers RDS(on) = 2.55 mΩ at VGS = 4.5 V - well within specification for reliable enhancement-mode operation with 3.3-V logic controllers when combined with appropriate gate driver buffering.
Is SIR866DP-T1-GE3 pin-compatible with standard SO-8 MOSFETs?
Yes, SIR866DP-T1-GE3 uses the PowerPAK SO-8 package with identical 6.15 mm × 5.15 mm footprint and pinout (G-S-S-S-D-D-D-D) as standard SO-8 - enabling direct substitution on existing SO-8 land patterns, though optimal thermal performance requires leveraging the exposed drain pad.
What does "100 % UIS Tested" mean for SIR866DP-T1-GE3?
"100 % UIS Tested" means every SIR866DP-T1-GE3 unit undergoes unclamped inductive switching stress testing per JEDEC JESD22-A110, verifying ability to withstand single-pulse avalanche energy up to 80 mJ and peak current of 40 A - ensuring robustness in DC-DC converter freewheeling phases where inductive energy must be absorbed by the MOSFET.
Can SIR866DP-T1-GE3 be used in OR-ing applications with back-to-back configuration?
Yes, SIR866DP-T1-GE3 is explicitly listed for OR-ing applications in its official Vishay documentation. Its low RDS(on) of 2.55 mΩ at VGS = 4.5 V, body diode VSD = 0.72–1.1 V, and 100 % UIS rating make it suitable for back-to-back N-channel configurations controlled by dedicated OR-ing controllers such as the LTC4359 or MAX5974.
SIR866DP-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® SO-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 20 V
- Current - Continuous Drain (Id) @ 25°C:
- 60A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 1.9mOhm @ 20A, 10V
- Vgs(th) (Max) @ Id:
- 2.3V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 107 nC @ 10 V
- Vgs (Max):
- ±20V
- Input Capacitance (Ciss) (Max) @ Vds:
- 4730 pF @ 10 V
- FET Feature:
- -
- Power Dissipation (Max):
- 5.4W (Ta), 83W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® SO-8
SIR866DP-T1-GE3 FAQ
1.How can I place an order for SIR866DP-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIR866DP-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIR866DP-T1-GE3 reliable?
The price and inventory of SIR866DP-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIR866DP-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIR866DP-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIR866DP-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIR866DP-T1-GE3?
SIR866DP-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIR866DP-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIR866DP-T1-GE3?
For technical support, including SIR866DP-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIR866DP-T1-GE3 requirements.
6.How does Aetrix verify that SIR866DP-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIR866DP-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIR866DP-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIR866DP-T1-GE3?
All SIR866DP-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIR866DP-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIR866DP-T1-GE3 part is unused and in its original packaging.
Return procedure for SIR866DP-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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