Vishay Siliconix SIS478DN-T1-GE3
- Part No.:
- SIS478DN-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® 1212-8
- Datasheet:
-
SIS478DN-T1-GE3.pdf
- Description:
- MOSFET N-CH 30V 12A PPAK1212-8
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SIS478DN-T1-GE3 from Vishay Siliconix is a N-channel 30 V (D-S) TrenchFET® Power MOSFET in PowerPAK 1212-8 package, with RDS(on) = 0.020 Ω at VGS = 10 V, 8 A; Qg = 3.6 nC at VGS = 4.5 V; and 100 % UIS tested - optimized for notebook PC system power and load switch applications.
For engineers reviewing the SIS478DN-T1-GE3 datasheet, SIS478DN-T1-GE3 pinout, SIS478DN-T1-GE3 application, or SIS478DN-T1-GE3 equivalent, key selection criteria include low gate charge for fast switching in high-frequency DC/DC converters, ultra-low RDS(on) at 4.5 V drive for efficient 5 V logic-level control, and PowerPAK 1212-8's 2.4 °C/W junction-to-case thermal resistance for compact thermal design.
Technical Context
This MOSFET uses trench-gate silicon technology to achieve low on-resistance and fast switching with minimal gate drive requirements. Its 30 V VDS rating and 12 A continuous drain current (TC = 25 °C) support mid-voltage load switching in portable computing power rails.
The device integrates 100 % Rg testing and 100 % UIS (unclamped inductive switching) validation, ensuring robustness under transient overcurrent conditions. Its gate threshold voltage range (1.2–2.5 V) enables reliable turn-on with standard 3.3 V or 5 V logic drivers without external level shifting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - supports input rails up to 24 V nominal with margin for transients in notebook system power. |
| RDS(on) @ VGS = 10 V | 0.020 Ω - enables <160 mW conduction loss at 8 A, critical for thermally constrained PCB layouts. |
| RDS(on) @ VGS = 4.5 V | 0.030 Ω - ensures full enhancement with 5 V microcontroller GPIOs, eliminating need for gate driver ICs. |
| Qg @ VGS = 4.5 V | 3.6 nC - reduces switching energy and gate drive power, supporting >1 MHz operation in point-of-load regulators. |
| TJ max | 150 °C - allows sustained operation in high-ambient environments like laptop chassis near CPU/GPU zones. |
| RthJC | 6.5 °C/W (typ.) - enables direct heat transfer from die to PCB copper, achieving 4.8 °C rise above board at 2 W dissipation. |
| Package | PowerPAK 1212-8 - 3.3 mm × 3.3 mm footprint, 40 % smaller than TSSOP-8, with exposed drain pad for thermal performance. |
Pinout & Package
PowerPAK 1212-8 is a leadless surface-mount package with an exposed drain pad on the bottom side. The top-side terminals are arranged in an 8-pin configuration: pins 1–4 are source (S), pin 5 is gate (G), and pins 6–8 are drain (D). The package height is 1.05 mm, enabling ultra-thin notebook designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–4 (S) | Source | Four parallel source connections reduce source inductance and improve current sharing in high-di/dt switching. |
| 5 (G) | Gate | Single gate terminal with 0.5–4.8 Ω gate resistance - compatible with standard logic-level drivers without added series resistance. |
| 6–8 (D) | Drain | Three drain terminals tied to large bottom-side exposed pad - provides low-inductance, high-current path to PCB ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® architecture | Delivers 0.020 Ω RDS(on) at 10 V in 3.3 mm × 3.3 mm footprint - 2× die area vs. TSOP-6, enabling higher current density. |
| 100 % UIS tested | Guarantees survival of 10 mJ single-pulse avalanche energy - eliminates need for external snubbers in inductive load switching. |
| 100 % Rg tested | Ensures gate resistance between 0.5–4.8 Ω - prevents oscillation and enables predictable turn-on/turn-off timing in high-speed circuits. |
| Halogen-free & RoHS-compliant | Meets IEC 61249-2-21 and Directive 2002/95/EC - supports environmental compliance for global notebook OEM shipments. |
| Exposed drain pad | Provides 2.4 °C/W junction-to-case thermal resistance - allows PCB copper to act as primary heatsink, reducing need for thermal vias. |
Applications
| Notebook System Power | USB-C Load Switch |
|---|---|
|
Use Scenario: Main 5 V/3.3 V system rail distribution in ultrabook motherboards, where space and thermal headroom are severely limited. IC Role / Device Role: High-side load switch controlling power delivery to memory, I/O controllers, and peripheral subsystems. Use Value: 0.030 Ω RDS(on) at 4.5 V enables <120 mW loss at 2 A, minimizing local heating and simplifying thermal management. |
Use Scenario: Hot-swap protection and power sequencing for USB-C PD ports in thin-and-light laptops. IC Role / Device Role: Low-side or high-side eFuse replacement with integrated overcurrent and thermal shutdown capability. Use Value: 100 % UIS rating handles 10 mJ inductive kickback during cable insertion, preventing latch-up or failure without external clamping. |
| GPU Core Voltage Sequencing | SSD Power Gate |
|
Use Scenario: Controlled ramp-up of GPU core voltage (Vcore) during boot, requiring precise timing and low-loss switching. IC Role / Device Role: Pre-regulator switch enabling soft-start and sequencing coordination with PMIC outputs. Use Value: 3.6 nC Qg at 4.5 V allows clean, jitter-free turn-on with 10 kΩ pull-up, meeting tight ±100 µs sequencing windows. |
Use Scenario: Isolating NVMe SSD power domain during sleep states to meet Intel Modern Standby (S0ix) leakage targets. IC Role / Device Role: Low-leakage power gate placed between buck converter output and SSD VDD input. Use Value: 1 µA IDSS at 30 V ensures <10 µW standby loss per gate - critical for sub-2 mW platform idle power budgets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel 30 V power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si7401DN-T1-GE3 | RDS(on) = 0.025 Ω @ 4.5 V; Qg = 4.2 nC; same PowerPAK 1212-8 package and pinout. | Higher conduction loss at 5 V drive - suitable where gate drive voltage ≥ 4.5 V but efficiency margin is tighter. | Select when lower cost is prioritized and 0.005 Ω RDS(on) increase is acceptable in thermal budget. |
| DMN3025LSD-13 | RDS(on) = 0.025 Ω @ 4.5 V; Qg = 5.3 nC; SO-8 package (larger footprint, 40 °C/W RthJA). | Requires PCB redesign due to SO-8 footprint and higher thermal resistance - not drop-in for space-constrained layouts. | Choose only if legacy SO-8 layout reuse is mandatory and thermal derating to 5 A is acceptable. |
Compared with Si7401DN-T1-GE3, SIS478DN-T1-GE3 delivers 20 % lower RDS(on) and 14 % lower Qg, enabling higher efficiency and faster switching; versus DMN3025LSD-13, it offers 4× better thermal resistance and 30 % smaller footprint - critical for next-gen ultrabook power stages.
Availability
SIS478DN-T1-GE3 is available at Aetrix Electronics and suitable for notebook PC system power, USB-C load switching, and GPU voltage sequencing requiring stable component supply across high-volume consumer electronics production cycles.
Supply support for SIS478DN-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics for power management and signal conditioning.
The SIS478DN product line targets space- and thermally constrained portable computing applications, delivering high-current switching in minimal PCB area using advanced trench-gate silicon and PowerPAK packaging.
FAQ
What is the maximum continuous drain current for SIS478DN-T1-GE3 at 70 °C case temperature?
The SIS478DN-T1-GE3 supports 12 A continuous drain current at TC = 70 °C, as specified in its Absolute Maximum Ratings table. This rating is package-limited and assumes proper PCB copper area for thermal conduction. At ambient temperatures, derating applies - for example, 7.4 A at TA = 70 °C on a 1" × 1" FR4 board. The SIS478DN-T1-GE3 datasheet confirms this value under Note 'a' in the ID specification row.
Does SIS478DN-T1-GE3 support 3.3 V logic-level gate drive?
SIS478DN-T1-GE3 has a gate threshold voltage range of 1.2–2.5 V and delivers RDS(on) = 0.030 Ω at VGS = 4.5 V, making it fully compatible with 3.3 V logic systems when driven with sufficient current. While not fully enhanced at 3.3 V (RDS(on) rises to ~0.045 Ω), it remains functional for low-duty-cycle or low-current loads. For optimal performance, 4.5 V or 5 V drive is recommended. The SIS478DN-T1-GE3 transfer characteristics curve confirms usable ID > 5 A at VGS = 3.3 V.
What is the thermal resistance from junction to ambient for SIS478DN-T1-GE3 on a standard PCB?
The SIS478DN-T1-GE3 has a typical RthJA of 32 °C/W (maximum 39 °C/W) when mounted on a 1" × 1" FR4 board, per its Thermal Resistance Ratings table. This value assumes standard JEDEC test conditions. With extended copper pour on the drain pad, RthJA can improve to ~25 °C/W. The SIS478DN-T1-GE3 PowerPAK 1212-8 package achieves this via its exposed drain pad, which directly couples heat to the PCB - unlike SO-8 or TSSOP-8 alternatives.
Is SIS478DN-T1-GE3 suitable for reverse polarity protection?
Yes - SIS478DN-T1-GE3 can be used in reverse polarity protection circuits when configured as a low-side switch with source tied to ground and load connected between drain and supply. Its body diode forward voltage is 0.8–1.2 V at 5 A, and it supports 12 A continuous source-drain current. However, for high-efficiency reverse protection, a dedicated ideal diode controller or back-to-back MOSFET configuration is preferred to avoid body diode conduction losses. The SIS478DN-T1-GE3 datasheet explicitly lists "Load Switch" among its applications.
What reflow profile should be used for SIS478DN-T1-GE3?
SIS478DN-T1-GE3 requires a lead-free reflow profile with peak temperature of 240 °C (+5/−0 °C), time above 180 °C of 70–180 seconds, and maximum ramp-down rate of 6 °C/s. Vishay specifies this in document 73257, accessible via www.vishay.com/ppg?73257. The PowerPAK 1212-8 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1, meaning floor life is unlimited at ≤30 °C/85 % RH. The SIS478DN-T1-GE3 reflow guidelines are identical to those for other Vishay PowerPAK devices.
SIS478DN-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® 1212-8
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 12A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 20mOhm @ 8A, 10V
- Vgs(th) (Max) @ Id:
- 2.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 10.5 nC @ 10 V
- Vgs (Max):
- ±25V
- Input Capacitance (Ciss) (Max) @ Vds:
- 398 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 15.6W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® 1212-8
SIS478DN-T1-GE3 FAQ
1.How can I place an order for SIS478DN-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIS478DN-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIS478DN-T1-GE3 reliable?
The price and inventory of SIS478DN-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIS478DN-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIS478DN-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIS478DN-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIS478DN-T1-GE3?
SIS478DN-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIS478DN-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIS478DN-T1-GE3?
For technical support, including SIS478DN-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIS478DN-T1-GE3 requirements.
6.How does Aetrix verify that SIS478DN-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIS478DN-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIS478DN-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIS478DN-T1-GE3?
All SIS478DN-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIS478DN-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIS478DN-T1-GE3 part is unused and in its original packaging.
Return procedure for SIS478DN-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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