Vishay Siliconix SISHA18ADN-T1-GE3
- Part No.:
- SISHA18ADN-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- FETs, MOSFETs
- Package:
- PowerPAK® 1212-8SH
- Datasheet:
-
SISHA18ADN-T1-GE3.pdf
- Description:
- N-CHANNEL 30 V (D-S) MOSFET POWE
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SISHA18ADN-T1-GE3 from Vishay Siliconix is an N-channel 30 V TrenchFET® Gen IV power MOSFET in a PowerPAK® 1212-8SH package, delivering RDS(on) = 4.6 mΩ at VGS = 10 V and 7.0 mΩ at VGS = 4.5 V, with 60 A continuous drain current (TC = 25 °C), optimized for high-efficiency synchronous rectification in compact DC/DC converters.
For engineers reviewing the SISHA18ADN-T1-GE3 datasheet, SISHA18ADN-T1-GE3 pinout, SISHA18ADN-T1-GE3 application, or SISHA18ADN-T1-GE3 equivalent, key selection criteria include low gate charge (9.8 nC at 4.5 V), robust avalanche rating (15 A IAS, 11.25 mJ EAS), thermal performance (RthJC = 4.7 °C/W), and leadless PowerPAK 1212-8SH packaging for high-power-density board layouts.
Technical Context
This MOSFET employs trench-gate silicon technology with optimized cell pitch and reduced gate-drain charge (Qgd = 1.55 nC) to minimize switching losses in hard-switched and synchronous buck topologies. Its 100% Rg and UIS tested construction ensures gate robustness and unclamped inductive switching reliability under transient conditions.
The device features a low-threshold gate drive (VGS(th) = 1.0–2.5 V) compatible with 3.3 V and 5 V controllers, and integrated body diode with trr = 21–42 ns and Qrr = 21–42 nC, enabling efficient reverse recovery in high-frequency synchronous rectification circuits up to several MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS | 30 V - Maximum blocking voltage for 24 V input rail systems and VRM secondary-side applications |
| RDS(on) @ 10 V | 4.6 mΩ - Enables <1 W conduction loss at 20 A, critical for >95% efficiency in 12 V–1 V conversion stages |
| RDS(on) @ 4.5 V | 7.0 mΩ - Supports direct drive from standard PWM controller outputs without level-shifting |
| Qg @ 4.5 V | 9.8 nC - Reduces gate driver power consumption and enables fast turn-on (<30 ns td(on)) at 4.5 V logic levels |
| ID (continuous) | 60 A @ TC = 25 °C - Sustains high-current loads in server VRMs and GPU power delivery with external heatsinking |
| EAS | 11.25 mJ - Withstands energy transients in unregulated inductive loads without failure during startup or fault events |
| RthJC | 4.7 °C/W - Allows direct thermal coupling to PCB copper or heatsink for junction temperature control below 150 °C |
Pinout & Package
PowerPAK® 1212-8SH is a 3.3 mm × 3.3 mm × 0.9 mm leadless surface-mount package with exposed drain paddle on bottom side for enhanced thermal dissipation. The package uses copper leadframe with nickel-palladium-gold plating and is RoHS-compliant, halogen-free, and MSL Level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 (S) | Source | Common source connection for internal parallel cells; requires low-inductance PCB pour for optimal switching performance |
| 5, 6, 7, 8 (D) | Drain | Exposed drain paddle (bottom side) and top-side terminals form low-resistance, low-inductance drain path to ground plane |
| G (pin 1 top view) | Gate | Single gate terminal located at corner; layout must minimize gate loop inductance to suppress ringing during 10 A/ns dI/dt transitions |
Key Features
| Feature | Design Value |
|---|---|
| TrenchFET® Gen IV architecture | Reduces specific on-resistance by ~25% vs. prior generation, enabling higher current density in same footprint |
| 100% Rg and UIS tested | Guarantees gate oxide integrity and single-pulse avalanche survivability across full production lot |
| Low Qgd/Qg ratio (0.16) | Improves Miller immunity and reduces risk of false turn-on in high-dV/dt synchronous rectifier applications |
| Optimized body diode trr | 21–42 ns reverse recovery time minimizes switching loss and EMI in high-frequency synchronous rectification |
| PowerPAK 1212-8SH package | Enables 2× higher power density than SO-8 while maintaining compatibility with standard reflow profiles (peak 260 °C) |
Applications
| Server VRM Secondary Side | High-Density Telecom DC/DC |
|---|---|
Use Scenario: 48 V–12 V intermediate bus converter supplying CPU/GPU core rails in data center servers. IC Role / Device Role / Timing Role: Synchronous rectifier switch replacing Schottky diode in multiphase buck converter output stage. Use Value: 4.6 mΩ RDS(on) cuts conduction loss by >40% vs. comparable 5 mΩ SO-8 MOSFETs, improving full-load efficiency by 0.8–1.2%. | Use Scenario: 12 V–3.3 V point-of-load regulator in 5G base station power modules. IC Role / Device Role / Timing Role: High-side switch in isolated flyback or active clamp forward topology with 500 kHz–1 MHz switching. Use Value: 9.8 nC Qg at 4.5 V allows direct drive from microcontroller GPIO, eliminating gate driver IC and reducing BOM count. |
| GPU Power Delivery | Industrial PLC DC/DC |
Use Scenario: 12 V–0.8 V multiphase buck converter powering AI accelerator cards with >400 A peak load. IC Role / Device Role / Timing Role: Low-side synchronous rectifier in 3-phase interleaved configuration with phase-shifted gate timing. Use Value: 60 A continuous rating at TC = 25 °C supports >15 A per phase with minimal derating, enabling compact 12 mm × 12 mm per-phase layout. | Use Scenario: 24 V–5 V non-isolated buck converter in programmable logic controller I/O power supply. IC Role / Device Role / Timing Role: Main power switch operating continuously at 200 kHz with 100% duty cycle capability during brownout conditions. Use Value: 15 A IAS and 11.25 mJ EAS ensure reliable operation during motor stall-induced inductive kickback events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar N-channel power MOSFET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IRLHS6342TRPBF | RDS(on) = 5.2 mΩ @ 4.5 V; Qg = 11.5 nC; PowerPAK SO-8 package (larger footprint, higher RthJA) | Lower current density; less suitable for ultra-compact VRMs but easier manual rework due to gull-wing leads | Select when board-level repairability or legacy SO-8 footprint compatibility is prioritized over power density |
| DMTH3007LPSQ-13 | RDS(on) = 4.8 mΩ @ 4.5 V; Qg = 10.5 nC; PowerDI 3333 package with exposed drain; AEC-Q101 qualified | Automotive-qualified variant with tighter parametric distribution and extended temperature validation | Select for industrial control systems requiring automotive-grade reliability documentation and -40 °C to +150 °C guaranteed operation |
Compared with IRLHS6342TRPBF and DMTH3007LPSQ-13, the SISHA18ADN-T1-GE3 delivers the lowest RDS(on) × Qg figure-of-merit (34.3 mΩ·nC) among the three, making it optimal for high-frequency, high-efficiency synchronous rectification where both conduction and switching losses must be minimized simultaneously.
Availability
SISHA18ADN-T1-GE3 is available at Aetrix Electronics and suitable for server VRMs, telecom DC/DC converters, and industrial PLC power supplies requiring stable component supply, long-term lifecycle support, and traceable sourcing from Vishay-authorized channels.
Supply support for SISHA18ADN-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors, specializing in high-performance MOSFETs, diodes, and optoelectronics with vertical manufacturing and rigorous reliability testing.
The SISHA18ADN-T1-GE3 belongs to Vishay's TrenchFET® Gen IV power MOSFET family, engineered specifically for high-current, high-frequency synchronous rectification in space-constrained computing and communications power systems.
FAQ
What is the maximum continuous drain current rating for SISHA18ADN-T1-GE3 at case temperature of 70 °C?
The SISHA18ADN-T1-GE3 supports 48 A continuous drain current at TC = 70 °C, as specified in the Absolute Maximum Ratings table. This derating reflects thermal limits of the PowerPAK 1212-8SH package and must be validated against actual PCB copper area and airflow in the target application. The SISHA18ADN-T1-GE3 datasheet confirms this value under steady-state conditions with proper heatsinking.
Does SISHA18ADN-T1-GE3 have a specified avalanche energy rating, and how is it tested?
Yes, the SISHA18ADN-T1-GE3 has a single-pulse avalanche energy rating of 11.25 mJ at L = 0.1 mH, with corresponding IAS = 15 A. It undergoes 100% unclamped inductive switching (UIS) testing per JEDEC JESD24-11, ensuring each unit survives rated avalanche stress without parameter shift or functional failure. This rating is explicitly documented in the Absolute Maximum Ratings section of the SISHA18ADN-T1-GE3 datasheet.
What is the gate threshold voltage range for SISHA18ADN-T1-GE3, and how does it vary with temperature?
The SISHA18ADN-T1-GE3 has a gate-source threshold voltage VGS(th) of 1.0–2.5 V at TJ = 25 °C and ID = 250 μA, with a negative temperature coefficient of −4.6 mV/°C. As junction temperature rises, VGS(th) decreases linearly-e.g., to ~0.7 V at 125 °C-enabling stable turn-on margin in high-temperature environments. This behavior is verified in the SISHA18ADN-T1-GE3 specifications table and typical characteristics plots.
Can SISHA18ADN-T1-GE3 be used with 3.3 V gate drive, and what is its RDS(on) under that condition?
Yes, the SISHA18ADN-T1-GE3 is fully characterized for 4.5 V gate drive and functions reliably with 3.3 V logic, though RDS(on) increases to approximately 9.5 mΩ (extrapolated from 4.5 V/7.0 mΩ and 10 V/4.6 mΩ curves). The SISHA18ADN-T1-GE3 datasheet specifies RDS(on) = 7.0 mΩ max at VGS = 4.5 V, confirming strong enhancement-mode operation well within 3.3 V-compatible controller margins.
What is the thermal resistance from junction to case (RthJC) for SISHA18ADN-T1-GE3, and how should it be applied in thermal design?
The SISHA18ADN-T1-GE3 has a maximum junction-to-case thermal resistance RthJC of 4.7 °C/W, measured from die junction to the exposed drain paddle. In thermal design, this value is used with the case temperature (measured at the PCB copper under the drain pad) to calculate worst-case junction temperature: TJ = TC + (Ptot × RthJC). The SISHA18ADN-T1-GE3 datasheet provides this parameter in the Thermal Resistance Ratings table and recommends soldering the drain paddle directly to ≥1 in² of 2 oz copper for optimal performance.
SISHA18ADN-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- TrenchFET®
- Package/Case:
- PowerPAK® 1212-8SH
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- FET Type:
- N-Channel
- Technology:
- MOSFET (Metal Oxide)
- Drain to Source Voltage (Vdss):
- 30 V
- Current - Continuous Drain (Id) @ 25°C:
- 22A (Ta), 60A (Tc)
- Drive Voltage (Max Rds On, Min Rds On):
- 4.5V, 10V
- Rds On (Max) @ Id, Vgs:
- 4.6mOhm @ 10A, 10V
- Vgs(th) (Max) @ Id:
- 2.5V @ 250µA
- Gate Charge (Qg) (Max) @ Vgs:
- 33 nC @ 10 V
- Vgs (Max):
- +20V, -16V
- Input Capacitance (Ciss) (Max) @ Vds:
- 1650 pF @ 15 V
- FET Feature:
- -
- Power Dissipation (Max):
- 3.5W (Ta), 26.5W (Tc)
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® 1212-8SH
SISHA18ADN-T1-GE3 FAQ
1.How can I place an order for SISHA18ADN-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SISHA18ADN-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SISHA18ADN-T1-GE3 reliable?
The price and inventory of SISHA18ADN-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SISHA18ADN-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SISHA18ADN-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SISHA18ADN-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SISHA18ADN-T1-GE3?
SISHA18ADN-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SISHA18ADN-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SISHA18ADN-T1-GE3?
For technical support, including SISHA18ADN-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SISHA18ADN-T1-GE3 requirements.
6.How does Aetrix verify that SISHA18ADN-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SISHA18ADN-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SISHA18ADN-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SISHA18ADN-T1-GE3?
All SISHA18ADN-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SISHA18ADN-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SISHA18ADN-T1-GE3 part is unused and in its original packaging.
Return procedure for SISHA18ADN-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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